STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
List of figures
Figure 49. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 50. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 240
Figure 51. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 52. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 257
Figure 53. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 257
Figure 54. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 55. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 56. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 57. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 58. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 259
Figure 59. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 260
Figure 60. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 61. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 62. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 63. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 64. Counter timing diagram, update event when repetition counter is not used. . . . . . . . . . . 262
Figure 65. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 263
Figure 66. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 67. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 264
Figure 68. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 69. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 264
Figure 70. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 265
Figure 71. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 266
Figure 72. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 73. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 74. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 75. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 76. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 77. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 270
Figure 78. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 79. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 80. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 81. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 82. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 83. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 84. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 85. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 86. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 278
Figure 87. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 279
Figure 88. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 89. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Figure 90. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 91. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 92. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 93. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 287
Figure 94. Example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 95. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 96. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 97. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 98. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 99. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 100. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 322
Doc ID 13902 Rev 9 31/995