STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 8.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) Address offset: 0x10 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 8.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) Address offset: 0x14 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 12 to 15) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 166/995 Doc ID 13902 Rev 9
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.5 GPIO and AFIO register maps Refer to Table 1 on page 41 for the register boundary addresses. The following tables give the GPIO and AFIO register map and the reset values. Table 50. GPIO register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 GPIOx_CRL CNF7 [1:0] MODE7 [1:0] CNF6 [1:0] MODE6 [1:0] CNF5 MODE5 CNF4 [1:0] [1:0] [1:0] MODE4 [1:0] CNF3 MODE3 CNF2 MODE2 [1:0] [1:0] [1:0] [1:0] CNF1 MODE1 CNF0 MODE0 [1:0] [1:0] [1:0] [1:0] 0x04 0x08 Reset value 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 GPIOx_CRH CNF 15 [1:0] MODE1 5 [1:0] CNF 14 [1:0] MODE1 4 [1:0] CNF 13 [1:0] MODE1 3 [1:0] CNF 12 [1:0] MODE1 2 [1:0] CNF 11 [1:0] MODE1 1 [1:0] CNF 10 [1:0] MODE1 0 [1:0] CNF MODE9 9 [1:0] [1:0] Reset value 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 CNF 8 [1:0] MODE8 [1:0] GPIOx_IDR IDR[15:0]l Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0C GPIOx_ODR ODR[15:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 0x14 0x18 GPIOx_BSRR BR[15:0] BSR[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_BRR BR[15:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_LCKR Reserved LCKK LCK[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 51. AFIO register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 0x04 0x04 0x08 0x0C AFIO_EVCR PORT[2:0] PIN[3:0] Reserved Reset value 0 0 0 0 0 0 0 AFIO_MAPR low-, mediumand high-density devices Reserved SWJ_CFG[2] SWJ_CFG[1] SWJ_CFG[0] Reserved ADC2_ETRGREG_REMAP ADC2_ETRGINJ_REMAP ADC1_ETRGREG_REMAP ADC1_ETRGINJ_REMAP TIM5CH4_IREMAP PD01_REMAP CAN1_REMAP[1] CAN1_REMAP[0] TIM4_REMPAP TIM3_REMPAP[1] TIM3_REMPAP[0] TIM2_REMPAP[1] TIM2_REMPAP[0] TIM1_REMPAP[1] TIM1_REMPAP[0] USART3_REMAP[1] USART3_REMAP[0] USART2_REMAP USART1_REMAP I2C1_REMAP SPI1_REMAP Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFIO_MAPR connectivity line devices Reserved PTP_PPS_REMAP TIM2ITR1_IREMAP SPI3_REMAP Reserved SWJ_CFG[2] SWJ_CFG[1] SWJ_CFG[0] MII_RMII_SEL CAN2_REMAP ETH_REMAP Reserved TIM5CH4_IREMAP PD01_REMAP CAN1_REMAP[1] CAN1_REMAP[0] TIM4_REMPAP TIM3_REMPAP[1] TIM3_REMPAP[0] TIM2_REMPAP[1] TIM2_REMPAP[0] TIM1_REMPAP[1] TIM1_REMPAP[0] USART3_REMAP[1] USART3_REMAP[0] USART2_REMAP USART1_REMAP I2C1_REMAP SPI1_REMAP Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFIO_EXTICR1 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFIO_EXTICR2 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVOE Doc ID 13902 Rev 9 167/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Real-time clock (RTC) RTC pr
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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