STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

USB on-the-go full-speed (OTG_FS)
RM0008
Figure 271. Receive FIFO read task
Start
No
RXFLVL
interrupt
Yes
Unmask RXFLVL
interrupt
Mask RXFLVL
interrupt
Unmask RXFLVL
interrupt
Read the received
packet from the
Receive FIFO
Read
OTG_FS_GRXSTSP
PKTSTS
0b0010
No
Yes
Yes
BCNT > 0
No
ai15674
●
●
Bulk and control OUT/SETUP transactions
A typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in
Figure 272. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control
SETUP transaction operates in the same way but has only one packet. The
assumptions are:
– The application is attempting to send two maximum-packet-size packets (transfer
size = 1, 024 bytes).
– The non-periodic transmit FIFO can hold two packets (128 KB for FS).
– The non-periodic request queue depth = 4.
Normal bulk and control OUT/SETUP operations
The sequence of operations in Figure 272 (channel 1) is as follows:
a) Initialize channel 1
b) Write the first packet for channel 1
c) Along with the last DWORD write, the core writes an entry to the non-periodic
request queue
d) As soon as the non-periodic queue becomes non-empty, the core attempts to
send an OUT token in the current frame
e) Write the second (last) packet for channel 1
f) The core generates the XFRC interrupt as soon as the last transaction is
completed successfully
g) In response to the XFRC interrupt, de-allocate the channel for other transfers
h) Handling non-ACK responses
796/995 Doc ID 13902 Rev 9