STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Advanced-control timers (TIM1&TIM8)
Figure 56. Counter timing diagram, internal clock divided by 4
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
0035 0036
0000 0001
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 57.
Counter timing diagram, internal clock divided by N
CK_PSC
Timer clock = CK_CNT
Counter register 1F 20
00
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 58.
Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
31
32 33 34 35 36 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register FF 36
Write a new value in TIMx_ARR
Doc ID 13902 Rev 9 259/995