29.01.2015 Views

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

General-purpose timer (TIMx)<br />

RM0008<br />

Table 78. TIMx register map <strong>and</strong> reset values (continued)<br />

Offset Register<br />

0x1C<br />

TIMx_CCMR2<br />

Output Compare<br />

mode<br />

31<br />

30<br />

29<br />

28<br />

27<br />

26<br />

25<br />

24<br />

23<br />

22<br />

21<br />

20<br />

19<br />

18<br />

17<br />

16<br />

15<br />

14<br />

13<br />

12<br />

11<br />

10<br />

9<br />

8<br />

7<br />

6<br />

5<br />

4<br />

3<br />

2<br />

1<br />

0<br />

OC4M CC4S OC3M CC3S<br />

Reserved<br />

[2:0]<br />

[1:0] [2:0]<br />

[1:0]<br />

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br />

TIMx_CCMR2<br />

IC4<br />

IC3<br />

CC4S<br />

CC3S<br />

Input Capture<br />

IC4F[3:0] PSC<br />

IC3F[3:0] PSC<br />

Reserved<br />

[1:0]<br />

[1:0]<br />

mode<br />

[1:0]<br />

[1:0]<br />

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br />

O24CE<br />

OC4PE<br />

OC4FE<br />

OC3CE<br />

OC3PE<br />

OC3FE<br />

0x20<br />

0x24<br />

0x28<br />

0x2C<br />

0x30<br />

TIMx_CCER<br />

Reserved<br />

CC4P<br />

CC4E<br />

Reserved<br />

CC3P<br />

CC3E<br />

Reserved<br />

CC2P<br />

CC2E<br />

Reset value 0 0 0 0 0 0 0 0<br />

TIMx_CNT<br />

CNT[15:0]<br />

Reserved<br />

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br />

TIMx_PSC<br />

PSC[15:0]<br />

Reserved<br />

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br />

TIMx_ARR<br />

ARR[15:0]<br />

Reserved<br />

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br />

Reserved<br />

Reserved<br />

CC1P<br />

CC1E<br />

0x34<br />

0x38<br />

0x3C<br />

0x40<br />

0x44<br />

TIMx_CCR1<br />

CCR1[15:0]<br />

Reserved<br />

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br />

TIMx_CCR2<br />

CCR2[15:0]<br />

Reserved<br />

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br />

TIMx_CCR3<br />

CCR3[15:0]<br />

Reserved<br />

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br />

TIMx_CCR4<br />

CCR4[15:0]<br />

Reserved<br />

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br />

Reserved<br />

0x48<br />

0x4C<br />

TIMx_DCR<br />

DBL[4:0]<br />

DBA[4:0]<br />

Reserved<br />

Reserved<br />

Reset value 0 0 0 0 0 0 0 0 0 0<br />

TIMx_DMAR<br />

DMAB[15:0]<br />

Reserved<br />

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0<br />

Refer to Table 1 on page 41 for the register boundary addresses.<br />

374/995 Doc ID 13902 Rev 9

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!