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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

USB on-the-go full-speed (OTG_FS)<br />

26.2.1 General features<br />

The OTG_FS interface:<br />

● is USB-IF certified to the Universal Serial Bus Specification Rev 2.0<br />

●<br />

●<br />

●<br />

●<br />

●<br />

●<br />

includes full support (PHY) for the optional On-The-Go (OTG) protocol detailed in the<br />

On-The-Go Supplement Rev 1.3 specification<br />

– integrated support for A-B Device Identification (ID line)<br />

– integrated support for Host Negotiation Protocol (HNP) <strong>and</strong> Session Request<br />

Protocol (SRP)<br />

– allows host to turn VBUS off to conserve battery power in OTG applications<br />

– supports OTG monitoring of VBUS levels with internal comparators<br />

– supports dynamic Host-Peripheral switch of role<br />

is software-configurable to operate as:<br />

– SRP capable USB FS Peripheral (B-Device)<br />

– SRP capable USB FS/LS Host (A-Device)<br />

– USB On-The-Go Full-Speed Dual Role Device<br />

supports FS SOF <strong>and</strong> LS Keep-alives with<br />

– SOF pulse PAD connectivity<br />

– SOF pulse internal connection to timer2 (TIM2)<br />

– configurable framing period<br />

– configurable end of frame interrupt<br />

includes power saving features such as system stop during USB Suspend, switch-off of<br />

clock domains internal to the digital core, PHY <strong>and</strong> DFIFO power management<br />

features a dedicated RAM of 1.25 Kbytes with advanced FIFO control:<br />

– configurable partitioning of RAM space into different FIFOs for flexible <strong>and</strong> efficient<br />

use of RAM<br />

– each FIFO can hold multiple packets<br />

– dynamic memory allocation<br />

– configurable FIFO sizes that are not powers of 2 to allow the use of contiguous<br />

memory locations<br />

guarantees max USB b<strong>and</strong>width for up to one frame (1ms) withouth system<br />

intervention<br />

26.2.2 Host-mode features<br />

The OTG_FS interface:<br />

● requires an external charge pump to generate the V BUS voltage<br />

● has up to 8 host channels (pipes) <strong>and</strong> each channel is dynamically reconfigurable to<br />

allocate any type of USB transfer<br />

● has a built-in HW scheduler holding:<br />

– up to 8 interrupt plus isochronous transfer requests in the periodic hardware<br />

queue<br />

– up to 8 control plus bulk transfer requests in the non-periodic hardware queue<br />

● manages a shared RX FIFO, a periodic TX FIFO <strong>and</strong> a nonperiodic TX FIFO for<br />

efficient usage of the USB data RAM<br />

Doc ID 13902 Rev 9 695/995

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