STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 294. MAC frame format 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 46-1500 bytes 4 bytes Preamble SFD Destination address Source address MAC client length/type MAC client data PAD Frame check sequence Bytes within frame transmitted top to bottom MSB LSB Bit transmission order (right to left) ai15629 Figure 295. Tagged MAC frame format 7 bytes 1 byte 6 bytes 6 bytes QTag Prefix 4 bytes 2 bytes 42-1500 bytes 4 bytes Preamble SFD Destination address Source address Length/type = 802.1QTagType Tag control information MAC client length/type MAC client data Pad Frame check sequence bytes within frame transmitted top to bottom MSB 1 0 0 0 0 0 0 0 1 User priority CFI VLAN identifier (VID, 12 bits) LSB 0 0 0 0 0 0 0 0 0 MSB Bit transmission order (right to left) LSB ai15630 Each byte of the MAC frame, except the FCS field, is transmitted low-order bit first. An invalid MAC frame is defined by one of the following conditions: ● The frame length is inconsistent with the expected value as specified by the length/type field. If the length/type field contains a type value, then the frame length is assumed to be consistent with this field (no invalid frame) ● The frame length is not an integer number of bytes (extra bits) ● The CRC value computed on the incoming frame does not match the included FCS 852/995 Doc ID 13902 Rev 9
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller 27.5.2 MAC frame transmission The DMA controls all transactions for the transmit path. Ethernet frames read from the system memory are pushed into the FIFO by the DMA. The frames are then popped out and transferred to the MAC core. When the end-of-frame is transferred, the status of the transmission is taken from the MAC core and transferred back to the DMA. The Transmit FIFO has a depth of 2 Kbyte. FIFO-fill level is indicated to the DMA so that it can initiate a data fetch in required bursts from the system memory, using the AHB interface. The data from the AHB Master interface is pushed into the FIFO. When the SOF is detected, the MAC accepts the data and begins transmitting to the MII. The time required to transmit the frame data to the MII after the application initiates transmission is variable, depending on delay factors like IFG delay, time to transmit preamble/SFD, and any back-off delays for Half-duplex mode. After the EOF is transferred to the MAC core, the core completes normal transmission and then gives the status of transmission back to the DMA. If a normal collision (in Half-duplex mode) occurs during transmission, the MAC core makes the transmit status valid, then accepts and drops all further data until the next SOF is received. The same frame should be retransmitted from SOF on observing a Retry request (in the Status) from the MAC. The MAC issues an underflow status if the data are not provided continuously during the transmission. During the normal transfer of a frame, if the MAC receives an SOF without getting an EOF for the previous frame, then the SOF is ignored and the new frame is considered as the continuation of the previous frame. There are two modes of operation for popping data towards the MAC core: ● In Threshold mode, as soon as the number of bytes in the FIFO crosses the configured threshold level (or when the end-of-frame is written before the threshold is crossed), the data is ready to be popped out and forwarded to the MAC core. The threshold level is configured using the TTC bits of ETH_DMABMR. ● In Store-and-forward mode, only after a complete frame is stored in the FIFO, the frame is popped towards the MAC core. If the Tx FIFO size is smaller than the Ethernet frame to be transmitted, then the frame is popped towards the MAC core when the Tx FIFO becomes almost full. The application can flush the Transmit FIFO of all contents by setting the FTF (ETH_DMAOMR register [20]) bit. This bit is self-clearing and initializes the FIFO pointers to the default state. If the FTF bit is set during a frame transfer to the MAC core, then transfer is stopped as the FIFO is considered to be empty. Hence an underflow event occurs at the MAC transmitter and the corresponding Status word is forwarded to the DMA. Automatic CRC and pad generation When the number of bytes received from the application falls below 60 (DA+SA+LT+Data), zeros are appended to the transmitting frame to make the data length exactly 46 bytes to meet the minimum data field requirement of IEEE 802.3. The MAC can be programmed not to append any padding. The cyclic redundancy check (CRC) for the frame check sequence (FCS) field is calculated and appended to the data being transmitted. When the MAC is programmed to not append the CRC value to the end of Ethernet frames, the computed CRC is not transmitted. An exception to this rule is that when the MAC is programmed to append pads for frames (DA+SA+LT+Data) less than 60 bytes, CRC will be appended at the end of the padded frames. Doc ID 13902 Rev 9 853/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) transfe
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RM0008 DMA controller (DMA) not sup
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Real-time clock (RTC) RTC pr
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Controller area network (bxC
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RM0008 Serial peripheral interface
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RM0008 Universal synchronous asynch
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RM0008 Device electronic signature
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Debug support (DBG) Note: On
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RM0008 Debug support (DBG) DBGMCU_I
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RM0008 Debug support (DBG) Table 20
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) 29.17.9
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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