STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Ethernet (ETH): media access control (MAC) with DMA controller
RM0008
Table 193.
Bit 18:
Ethernet frame
Frame statuses
Bit 27: Header
checksum error
Bit 28: Payload
checksum error
Frame status
0 0 0
1 0 0
1 0 1
1 1 0
1 1 1
0 0 1
0 1 1
0 1 0 Reserved
The frame is an IEEE 802.3 frame (Length
field value is less than 0x0600).
IPv4/IPv6 Type frame in which no checksum
error is detected.
IPv4/IPv6 Type frame in which a payload
checksum error (as described for PCE) is
detected
IPv4/IPv6 Type frame in which IP header
checksum error (as described for IPCO HCE)
is detected.
IPv4/IPv6 Type frame in which both PCE and
IPCO HCE are detected.
IPv4/IPv6 Type frame in which there is no IP
HCE and the payload check is bypassed due
to unsupported payload.
Type frame which is neither IPv4 or IPv6
(checksum offload bypasses the checksum
check completely)
Receive frame controller
If the RA bit is reset in the MAC CSR frame filter register, the MAC performs frame filtering
based on the destination/source address (the application still needs to perform another level
of filtering if it decides not to receive any bad frames like runt, CRC error frames, etc.). On
detecting a filter-fail, the frame is dropped and not transferred to the application. When the
filtering parameters are changed dynamically, and in case of (DA-SA) filter-fail, the rest of
the frame is dropped and the Rx Status Word is immediately updated (with zero frame
length, CRC error and Runt Error bits set), indicating the filter fail. In Ethernet power down
mode, all received frames are dropped, and are not forwarded to the application.
Receive flow control
The MAC detects the receiving Pause frame and pauses the frame transmission for the
delay specified within the received Pause frame (only in Full-duplex mode). The Pause
frame detection function can be enabled or disabled with the RFCE bit in ETH_MACFCR.
Once receive flow control has been enabled, the received frame destination address begins
to be monitored for any match with the multicast address of the control frame
(0x0180 C200 0001). If a match is detected (the destination address of the received frame
matches the reserved control frame destination address), the MAC then decides whether or
not to transfer the received control frame to the application, based on the level of the PCF bit
in ETH_MACFFR.
The MAC also decodes the type, opcode, and Pause Timer fields of the receiving control
frame. If the byte count of the status indicates 64 bytes, and if there is no CRC error, the
MAC transmitter pauses the transmission of any data frame for the duration of the decoded
Pause time value, multiplied by the slot time (64 byte times for both 10/100 Mbit/s modes).
862/995 Doc ID 13902 Rev 9