STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
USB on-the-go full-speed (OTG_FS)
Figure 265. OTG_FS controller block diagram
AHB slave interface
BIUS AHB slave
AIU
PSRAM
PFC
MAC
WPC
PIU
SIE
FS serial interface
ai15608
1. BIUS = bus interface unit, AIU = application interface unit, PFC = packet FIFO controller, MAC = media
access controller, WPC = wakeup and power controller, PIU = PHY interface unit, SIE = serial interface
engine.
The USB system features 1.25 Kbyte of dedicated RAM with a sophisticated FIFO control
mechanism. The packet FIFO controller (PFC) module in the OTG_FS Core organizes RAM
space into Tx-FIFOs into which the application pushes the data to be temporarily stored
before the USB transmission, and into a single Rx FIFO where the data received from the
USB are temporarily stored before retrieval (popped) by the application. The number of
instructed FIFOs and how these are architectured inside the RAM depends on the device’s
role. In peripheral mode an additional Tx-FIFO is instructed for each active IN endpoint. Any
FIFO size is software configured to better meet the application requirements.
Doc ID 13902 Rev 9 711/995