STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

General-purpose timer (TIMx)
RM0008
Figure 123. Control circuit in external clock mode 2
f MASTER
CNT_EN
ETR
ETRP
ETRF
Counter clock = CK_CNT = CK_PSC
Counter register 34
35 36
14.3.4 Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Figure 124. Capture/compare channel (example: channel 1 input stage)
TI1F_ED
to the slave mode controller
TI1F_Rising
TI1 0
filter
TI1F
Edge
f DTS downcounter
Detector TI1F_Falling
1
ICF[3:0]
TIMx_CCMR1
CC1P
TIMx_CCER
TI2F_rising
(from channel 2)
TI2F_falling
(from channel 2)
0
1
TI1FP1
TI2FP1
01
10
TRC
11
(from slave mode
controller)
CC1S[1:0]
IC1
ICPS[1:0]
TIMx_CCMR1
divider
/1, /2, /4, /8
CC1E
IC1PS
TIMx_CCER
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
334/995 Doc ID 13902 Rev 9