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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Universal synchronous asynchronous receiver transmitter (USART)<br />

RM0008<br />

The nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be<br />

added up to the mantissa<br />

DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33<br />

Then, USART_BRR = 0x330 hence USARTDIV = 0d51.000<br />

Table 174.<br />

Error calculation for programmed baud rates<br />

Baud rate f PCLK = 36 MHz f PCLK = 72 MHz<br />

S.No<br />

in<br />

Kbps<br />

Actual<br />

Value<br />

programmed<br />

in the Baud<br />

Rate register<br />

% Error<br />

=(Calculated -<br />

Desired)B.Rate<br />

/Desired B.Rate<br />

Actual<br />

Value<br />

programmed<br />

in the Baud<br />

Rate register<br />

% Error<br />

1. 2.4 2.400 937.5 0% 2.4 1875 0%<br />

2. 9.6 9.600 234.375 0% 9.6 468.75 0%<br />

3. 19.2 19.2 117.1875 0% 19.2 234.375 0%<br />

4. 57.6 57.6 39.0625 0% 57.6 78.125 0.%<br />

5. 115.2 115.384 19.5 0.15% 115.2 39.0625 0%<br />

6. 230.4 230.769 9.75 0.16% 230.769 19.5 0.16%<br />

7. 460.8 461.538 4.875 0.16% 461.538 9.75 0.16%<br />

8. 921.6 923.076 2.4375 0.16% 923.076 4.875 0.16%<br />

9. 2250 2250 1 0% 2250 2 0%<br />

10. 4500 NA NA NA 4500 1 0%<br />

Note: 1 The lower the CPU clock the lower will be the accuracy for a particular Baud rate. The upper<br />

limit of the achievable baud rate can be fixed with this data.<br />

2 Only USART1 is clocked with PCLK2 (72 MHz Max). Other USARTs are clocked with<br />

PCLK1 (36 MHz Max).<br />

25.3.5 USART receiver’s tolerance to clock deviation<br />

The USART’s asynchronous receiver works correctly only if the total clock system deviation<br />

is smaller than the USART receiver’s tolerance. The causes which contribute to the total<br />

deviation are:<br />

● DTRA: Deviation due to the transmitter error (which also includes the deviation of the<br />

transmitter’s local oscillator)<br />

●<br />

●<br />

DQUANT: Error due to the baud rate quantization of the receiver<br />

DREC: Deviation of the receiver’s local oscillator<br />

● DTCL: Deviation due to the transmission line (generally due to the transceivers which<br />

can introduce an asymmetry between the low-to-high transition timing <strong>and</strong> the high-tolow<br />

transition timing)<br />

DTRA + DQUANT + DREC + DTCL < USART receiver’s tolerance<br />

666/995 Doc ID 13902 Rev 9

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