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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Power control (PWR)<br />

4 Power control (PWR)<br />

Low-density devices are <strong>STM32F101xx</strong>, <strong>STM32F102xx</strong> <strong>and</strong> <strong>STM32F103xx</strong><br />

microcontrollers where the Flash memory density ranges between 16 <strong>and</strong> 32 Kbytes.<br />

Medium-density devices are <strong>STM32F101xx</strong>, <strong>STM32F102xx</strong> <strong>and</strong> <strong>STM32F103xx</strong><br />

microcontrollers where the Flash memory density ranges between 64 <strong>and</strong> 128 Kbytes.<br />

High-density devices are <strong>STM32F101xx</strong> <strong>and</strong> <strong>STM32F103xx</strong> microcontrollers where the<br />

Flash memory density ranges between 256 <strong>and</strong> 512 Kbytes.<br />

Connectivity line devices are <strong>STM32F105xx</strong> <strong>and</strong> STM32F107xx microcontrollers.<br />

This section applies to the whole STM32F10xxx family, unless otherwise specified.<br />

4.1 Power supplies<br />

The device requires a 2.0-to-3.6 V operating voltage supply (V DD ). An embedded regulator<br />

is used to supply the internal 1.8 V digital power.<br />

The real-time clock (RTC) <strong>and</strong> backup registers can be powered from the V BAT voltage when<br />

the main V DD supply is powered off.<br />

Figure 4.<br />

Power supply overview<br />

(V SSA ) V REF-<br />

(from 2.4 V up to V DDA ) V REF+<br />

(V DD ) V DDA<br />

(V SS ) V SSA<br />

V DDA domain<br />

A/D converter<br />

Temp. sensor<br />

Reset block<br />

PLL<br />

V SS<br />

V DD<br />

V DD domain<br />

I/O Ring<br />

St<strong>and</strong>by circuitry<br />

(Wakeup logic,<br />

IWDG)<br />

Voltage Regulator<br />

1.8 V domain<br />

Core<br />

Memories<br />

digital<br />

peripherals<br />

Low voltage detector<br />

V BAT<br />

Backup domain<br />

LSE crystal 32K osc<br />

BKP registers<br />

RCC BDCR register<br />

RTC<br />

Note: 1 V DDA <strong>and</strong> V SSA must be connected to V DD <strong>and</strong> V SS , respectively.<br />

Doc ID 13902 Rev 9 53/995

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