STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
USB on-the-go full-speed (OTG_FS)
26.10.2 Peripheral Tx FIFOs
The shared FIFO implementation is not viable for IN transactions. Pushing back-to-back
packets into a common Tx FIFO would require to know the host sequence in advance or to
predict it by a learning process. That is why in peripheral mode the core is configured to
have individual dedicated FIFOs for each IN endpoint. The application configures FIFO
sizes by writing the non periodic transmit FIFO size register (GNPTXFSIZ) for IN endpoint0
and the device IN endpoint transmit FIFOx registers (DIEPTXFx) for IN endpoint-x.
The dedicated transmit FIFO architecture is more flexible. It puts less load on the application
as there is no need for the application to predict the order in which the USB host is going to
access the IN endpoints.
Depending on the configured value of the non-periodic Tx FIFO empty level bit in the AHB
configuration register (TXFELVL bit in OTG_FS_GAHBCFG) the OTG_FS core indicates
that an IN endpoint Tx-FIFO is half or completely empty using the Tx FIFO empty interrupt
(NPTXFE bit in OTG_FS_GINTSTS). The application reads the device all endpoint interrupt
register (DAINT) to know which IN endpoint needs to be served. The application should
preliminarily check that enough free space is available by reading the device IN endpoint-x
transmit FIFO status register (DTXFSTSx). If so, the application then pushes the transmit
data into the Tx-FIFOn by writing to the endpoint-related push address.
26.11 Host FIFO architecture
Figure 267. Host-mode FIFO address mapping and AHB FIFO access mapping
Single data
FIFO
Any periodic channel
DFIFO push access
from AHB
MAC pop
Periodic Tx
FIFO control
(optional)
Periodic Tx packets
HPTXFSIZ[31:16]
HPTXFSIZ[15:0]
Any non-periodic
channel DFIFO push
access from AHB
MAC pop
Non-periodic
Tx FIFO control
Periodic Tx packets
NPTXFSIZ[31:16]
NPTXFSIZ[15:0]
Any channel DFIFO pop
access from AHB
MAC push
Rx FIFO control
Rx packets
RXFSIZ[31:16]
Rx start address
fixed to 0
A1 = 0
ai15610
26.11.1 Host Rx FIFO
The host uses one receiver FIFO for all periodic and nonperiodic transactions. The FIFO is
used as a receive buffer to hold the received data (payload of the received packet) from the
USB until it is transferred to the system memory. Packets received from any remote IN
endpoint are stacked back-to-back until free space is available. The status of each received
packet with the host channel destination, byte count, data PID and validity of the received
Doc ID 13902 Rev 9 713/995