STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

USB on-the-go full-speed (OTG_FS)
RM0008
26.8 Power options
The power consumption of the OTG PHY is controlled by three bits in the general core
configuration register:
● PHY power down (GCCFG/PWRDWN)
– switch on/off the full-speed transceiver module of the PHY. Must be preliminarily
set to allow any USB operation.
● A-V BUS sensing enable (GCCFG/VBUSASEN)
– switch on/off the V BUS comparators associated with A-Device operations. Must be
set when in A-Device (USB Host) mode and during HNP.
● B-V BUS sensing enable (GCCFG/VBUSASEN)
– switch on/off the V BUS comparators associated with B-Device operations. Must be
set when in B-Device (USB peripheral) mode and during HNP.
Power reduction techniques are available while in the USB suspended state, when the USB
session is not yet valid or the device is disconnected.
● Stop PHY clock (STPPCLK bit in OTG_FS_PCGCCTL)
– when setting the stop PHY clock bit in the clock gating control register, most of the
48 MHz clock domain internal to the OTG full-speed core is switched off by clock
gating. The dynamic power consumption due to the USB clock switching activity is
cut even if the 48 MHz clock input is kept running by the application
– most of the transceiver is also disabled, and only the part in charge of detecting
the asynchronous resume or remote wakeup event is kept alive.
● Gate HCLK (GATEHCLK bit in OTG_FS_PCGCCTL)
– when setting the Gate HCLK bit in the clock gating control register, most of the
system clock domain internal to the OTG_FS Core is switched off by clock gating.
Only the register read and write interface is kept alive. The dynamic power
consumption due to the USB clock switching activity is cut even if the system clock
is kept running by the application for other purposes.
● USB system stop
– When the OTG_FS is in the USB suspended state, the application may decide to
drastically reduce the overall power consumption by a complete shut down of all
the clock sources in the system. USB System Stop is activated by first setting the
Stop PHY clock bit and then configuring the system deep sleep mode in the power
control system module (PWR).
– The OTG_FS Core automatically reactivates both system and USB clocks by
asynchronous detection of remote wakeup (as an Host) or resume (as a Device)
signaling on the USB.
To save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS
Core.
26.9 USB data FIFOs
Figure 265 shows the OTG_FS controller blocks and their functions.
710/995 Doc ID 13902 Rev 9