STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Controller area network (bxCAN)
Figure 193. Dual CAN block diagram (connectivity devices)
Control/Status/Configuration
Master Control
Master Status
Tx Status
Rx FIFO 0 Status
Rx FIFO 1 Status
Interrupt Enable
Error Status
Bit Timing
Filter Master
Filter Mode
Filter Scale
Filter FIFO Assign
Filter Activation
CAN 2.0B Active Core
CAN1 (Master) with 512 bytes SRAM
Master
Tx Mailboxes
Mailbox 0
2
1
Transmission
Scheduler
Memory
Access
Controller
Transmission
Scheduler
Slave
Tx Mailboxes
Mailbox 0 1 2
Master
Receive FIFO 0
Mailbox 0 1 2
Filter 0
Acceptance Filters
1
Master Filters
(0 to n)
Slave
Receive FIFO 0
Mailbox 0 1 2
2
3
Master
Receive FIFO 1
Mailbox 0 1 2
..
..
26
Slave Filters
(n to 27)
Slave
Receive FIFO 1
Mailbox 0 1 2
27
CAN2 (Slave)
Control/Status/Configuration
Master Control
Master Status
Tx Status
Rx FIFO 0 Status
Rx FIFO 1 Status
Interrupt Enable
Error Status
Bit Timing
CAN 2.0B Active Core
Note: CAN 2 start filter bank number n is configurable by writing to
the CAN2SB[5:0] bits in the CAN_ FMR register.
ai16094
22.4 bxCAN operating modes
bxCAN has three main operating modes: initialization, normal and Sleep. After a
hardware reset, bxCAN is in Sleep mode to reduce power consumption and an internal pullup
is active on CANTX. The software requests bxCAN to enter initialization or Sleep mode
by setting the INRQ or SLEEP bits in the CAN_MCR register. Once the mode has been
entered, bxCAN confirms it by setting the INAK or SLAK bits in the CAN_MSR register and
the internal pull-up is disabled. When neither INAK nor SLAK are set, bxCAN is in normal
mode. Before entering normal mode bxCAN always has to synchronize on the CAN bus.
Doc ID 13902 Rev 9 545/995