STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Serial peripheral interface (SPI)
RM0008
CRC error
This flag is used to verify the validity of the value received when the CRCEN bit in the
SPI_CR1 register is set. The CRCERR flag in the SPI_SR register is set if the value
received in the shift register (after transmission of the transmitter SPI_TXCRCR value) does
not match the receiver SPI_RXCRCR value.
23.3.9 Disabling the SPI
Note:
When transfer is terminated, the application can stop the communication by disabling the
SPI peripheral. This is done by resetting the SPE bit. Disabling the SPI peripheral while the
last data transfer is still ongoing does not affect the data reliability if the device is not in
Master transmit mode.
In Master transmit mode (full-duplex or simplex transmit only), the application must make
sure that no data transfer is ongoing by checking the BSY flag in the SPI_SR register before
disabling the SPI master.
23.3.10 SPI interrupts
Table 165.
SPI interrupt requests
Interrupt event Event flag Enable Control bit
Transmit buffer empty flag TXE TXEIE
Receive buffer not empty flag RXNE RXNEIE
Master Mode fault event
Overrun error
CRC error flag
MODF
OVR
CRCERR
ERRIE
23.4 I 2 S functional description
The I 2 S audio protocol is not available in low- and medium-density devices. This section
concerns only high-density and connectivity line devices.
23.4.1 General description
The block diagram of the I 2 S is shown in Figure 211.
598/995 Doc ID 13902 Rev 9