STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Universal serial bus full-speed device interface (USB)
RM0008
Table 152.
Double-buffering buffer flag definition
Buffer flag ‘Transmission’ endpoint ‘Reception’ endpoint
DTOG DTOG_TX (USB_EPnRbit 6) DTOG_RX (USB_EPnRbit 14)
SW_BUF USB_EPnR bit 14 USB_EPnR bit 6
The memory buffer which is currently being used by the USB peripheral is defined by DTOG
buffer flag, while the buffer currently in use by application software is identified by SW_BUF
buffer flag. The relationship between the buffer flag value and the used packet buffer is the
same in both cases, and it is listed in the following table.
Table 153.
Bulk double-buffering memory buffers usage
Endpoint
Type
DTOG SW_BUF
Packet buffer used by USB
Peripheral
Packet buffer used by
Application Software
0 1
ADDRn_TX_0 / COUNTn_TX_0
Buffer description table locations.
ADDRn_TX_1 / COUNTn_TX_1
Buffer description table locations.
IN
1 0
ADDRn_TX_1 / COUNTn_TX_1
Buffer description table locations
0 0 None (1)
ADDRn_TX_0 / COUNTn_TX_0
Buffer description table locations.
ADDRn_TX_0 / COUNTn_TX_0
Buffer description table locations.
1 1 None (1) ADDRn_TX_0 / COUNTn_TX_0
Buffer description table locations.
0 1
ADDRn_RX_0 / COUNTn_RX_0
Buffer description table locations.
ADDRn_RX_1 / COUNTn_RX_1
Buffer description table locations.
OUT
1 0
ADDRn_RX_1 / COUNTn_RX_1
Buffer description table locations.
ADDRn_RX_0 / COUNTn_RX_0
Buffer description table locations.
0 0 None (1) ADDRn_RX_0 / COUNTn_RX_0
Buffer description table locations.
1 1 None (1) ADDRn_RX_1 / COUNTn_RX_1
Buffer description table locations.
1. Endpoint in NAK Status.
Double-buffering feature for a bulk endpoint is activated by:
● Writing EP_TYPE bit field at ‘00’ in its USB_EPnR register, to define the endpoint as a
bulk, and
● Setting EP_KIND bit at ‘1’ (DBL_BUF), in the same register.
The application software is responsible for DTOG and SW_BUF bits initialization according
to the first buffer to be used; this has to be done considering the special toggle-only property
that these two bits have. The end of the first transaction occurring after having set
DBL_BUF, triggers the special flow control of double-buffered bulk endpoints, which is used
for all other transactions addressed to this endpoint until DBL_BUF remain set. At the end of
each transaction the CTR_RX or CTR_TX bit of the addressed endpoint USB_EPnR
register is set, depending on the enabled direction. At the same time, the affected DTOG bit
in the USB_EPnR register is hardware toggled making the USB peripheral buffer swapping
completely software independent. Unlike common transactions, and the first one after
522/995 Doc ID 13902 Rev 9