STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Ethernet DMA transmit poll demand register (ETH_DMATPDR) Address offset: 0x1004 Reset value: 0x0000 0000 This register is used by the application to instruct the DMA to poll the transmit descriptor list. The transmit poll demand register enables the Transmit DMA to check whether or not the current descriptor is owned by DMA. The Transmit Poll Demand command is given to wake up the TxDMA if it is in Suspend mode. The TxDMA can go into Suspend mode due to an underflow error in a transmitted frame or due to the unavailability of descriptors owned by transmit DMA. You can issue this command anytime and the TxDMA resets it once it starts re-fetching the current descriptor from host memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPD rw_wt Bits 31:0 TPD: Transmit poll demand When these bits are written with any value, the DMA reads the current descriptor pointed to by the ETH_DMACHTDR register. If that descriptor is not available (owned by Host), transmission returns to the Suspend state and ETH_DMASR register bit 2 is asserted. If the descriptor is available, transmission resumes. EHERNET DMA receive poll demand register (ETH_DMARPDR) Address offset: 0x1008 Reset value: 0x0000 0000 This register is used by the application to instruct the DMA to poll the receive descriptor list. The Receive poll demand register enables the receive DMA to check for new descriptors. This command is given to wake up the RxDMA from Suspend state. The RxDMA can go into Suspend state only due to the unavailability of descriptors owned by it. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RPD rw_wt Bits 31:0 RPD: Receive poll demand When these bits are written with any value, the DMA reads the current descriptor pointed to by the ETH_DMACHRDR register. If that descriptor is not available (owned by Host), reception returns to the Suspended state and ETH_DMASR register bit 7 is not asserted. If the descriptor is available, the Receive DMA returns to active state. 934/995 Doc ID 13902 Rev 9
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet DMA receive descriptor list address register (ETH_DMARDLAR) Address offset: 0x100C Reset value: 0x0000 0000 The Receive descriptor list address register points to the start of the receive descriptor list. The descriptor lists reside in the STM32F107xx's physical memory space and must be word-aligned. The DMA internally converts it to bus-width aligned address by making the corresponding LS bits low. Writing to the ETH_DMARDLAR register is permitted only when reception is stopped. When stopped, the ETH_DMARDLAR register must be written to before the receive Start command is given. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRL rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 SRL: Start of receive list This field contains the base address of the first descriptor in the receive descriptor list. The LSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by the DMA. Hence these LSB bits are read only. Ethernet DMA transmit descriptor list address register (ETH_DMATDLAR) Address offset: 0x1010 Reset value: 0x0000 0000 The Transmit descriptor list address register points to the start of the transmit descriptor list. The descriptor lists reside in the STM32F107xx's physical memory space and must be word-aligned. The DMA internally converts it to bus-width-aligned address by taking the corresponding LSB to low. Writing to the ETH_DMATDLAR register is permitted only when transmission has stopped. Once transmission has stopped, the ETH_DMATDLAR register can be written before the transmission Start command is given. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STL rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 STL: Start of transmit list This field contains the base address of the first descriptor in the transmit descriptor list. The LSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by the DMA. Hence these LSB bits are read-only. Ethernet DMA status register (ETH_DMASR) Address offset: 0x1014 Reset value: 0x0000 0000 The Status register contains all the status bits that the DMA reports to the application. The ETH_DMASR register is usually read by the software driver during an interrupt service routine or polling. Most of the fields in this register cause the host to be interrupted. The ETH_DMASR register bits are not cleared when read. Writing 1 to (unreserved) bits in Doc ID 13902 Rev 9 935/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) transfe
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RM0008 DMA controller (DMA) not sup
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Digital-to-analog converter
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RM0008 General-purpose timer (TIMx)
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Real-time clock (RTC) RTC pr
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Secure digital input/output
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RM0008 Controller area network (bxC
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RM0008 Serial peripheral interface
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RM0008 Inter-integrated circuit (I
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RM0008 Universal synchronous asynch
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RM0008 Ethernet (ETH): media access
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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