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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS)<br />

RM0008<br />

OTG_FS non-periodic transmit FIFO size register (OTG_FS_GNPTXFSIZ)<br />

Address offset: 0x028<br />

Reset value: 0x0000 0200<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

NPTXFD<br />

r/rw<br />

NPTXFSA<br />

r/rw<br />

Bits 31:16 NPTXFD: Non-periodic TxFIFO depth<br />

This value is in terms of 32-bit words.<br />

Minimum value is 16<br />

Maximum value is 256<br />

Bits 15:0 NPTXFSA: Non-periodic transmit RAM start address<br />

This field contains the memory start address for non-periodic transmit FIFO RAM.<br />

OTG_FS non-periodic transmit FIFO/queue status register<br />

(OTG_FS_GNPTXSTS)<br />

Note:<br />

Address offset: 0x02C<br />

Reset value: 0x0008 0200<br />

In Device mode, this register is not valid.<br />

This read-only register contains the free space information for the non-periodic TxFIFO <strong>and</strong><br />

the non-periodic transmit request queue.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved<br />

NPTXQTOP NPTQXSAV NPTXFSAV<br />

r r r<br />

Bit 31 Reserved<br />

Bits 30:24 NPTXQTOP: Top of the non-periodic transmit request queue<br />

Entry in the non-periodic Tx request queue that is currently being processed by the MAC.<br />

Bits [30:27]: Channel/endpoint number<br />

Bits [26:25]:<br />

– 00: IN/OUT token<br />

– 01: Zero-length transmit packet (device IN/host OUT)<br />

– 11: Channel halt comm<strong>and</strong><br />

Bit [24]: Terminate (last entry for selected channel/endpoint)<br />

740/995 Doc ID 13902 Rev 9

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