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Real-time clock (RTC) RM0008 16.3.2 Resetting RTC registers All system registers are asynchronously reset by a System Reset or Power Reset, except for RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV. The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup Domain reset. Refer to Section 6.1.3 on page 75. 16.3.3 Reading RTC registers The RTC core is completely independent from the RTC APB1 interface. Software accesses the RTC prescaler, counter and alarm values through the APB1 interface but the associated readable registers are internally updated at each rising edge of the RTC clock resynchronized by the RTC APB1 clock. This is also true for the RTC flags. This means that the first read to the RTC APB1 registers may be corrupted (generally read as 0) if the APB1 interface has previously been disabled and the read occurs immediately after the APB1 interface is enabled but before the first internal update of the registers. This can occur if: ● A system reset or power reset has occurred ● The MCU has just woken up from Standby mode (see Section 4.3: Low-power modes) ● The MCU has just woken up from Stop mode (see Section 4.3: Low-power modes) In all the above cases, the RTC core has been kept running while the APB1 interface was disabled (reset, not clocked or unpowered). Consequently when reading the RTC registers, after having disabled the RTC APB1 interface, the software must first wait for the RSF bit (Register Synchronized Flag) in the RTC_CRL register to be set by hardware. Note that the RTC APB1 interface is not affected by WFI and WFE low-power modes. 16.3.4 Configuring RTC registers To write in the RTC_PRL, RTC_CNT, RTC_ALR registers, the peripheral must enter Configuration Mode. This is done by setting the CNF bit in the RTC_CRL register. In addition, writing to any RTC register is only enabled if the previous write operation is finished. To enable the software to detect this situation, the RTOFF status bit is provided in the RTC_CR register to indicate that an update of the registers is in progress. A new value can be written to the RTC registers only when the RTOFF status bit value is ’1’. Configuration procedure: 1. Poll RTOFF, wait until its value goes to ‘1’ 2. Set the CNF bit to enter configuration mode 3. Write to one or more RTC registers 4. Clear the CNF bit to exit configuration mode 5. Poll RTOFF, wait until its value goes to ‘1’ to check the end of the write operation. The write operation only executes when the CNF bit is cleared; it takes at least three RTCCLK cycles to complete. 390/995 Doc ID 13902 Rev 9
RM0008 Real-time clock (RTC) 16.3.5 RTC flag assertion The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update of the RTC Counter. The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the counter reaches 0x0000. The RTC_Alarm and RTC Alarm flag (ALRF) (see Figure 156) are asserted on the last RTC Core clock cycle before the counter reaches the RTC Alarm value stored in the Alarm register increased by one (RTC_ALR + 1). The write operation in the RTC Alarm and RTC Second flag must be synchronized by using one of the following sequences: ● Use the RTC Alarm interrupt and inside the RTC interrupt routine, the RTC Alarm and/or RTC Counter registers are updated. ● Wait for SECF bit to be set in the RTC Control register. Update the RTC Alarm and/or the RTC Counter register. Figure 156. RTC second and alarm waveform example with PR=0003, ALARM=00004 RTCCLK RTC_PR 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 RTC_Second RTC_CNT 0000 0001 0002 0003 0004 0005 RTC_ALARM 1 RTCCLK ALRF (not powered in Standby) can be cleared by software Figure 157. RTC Overflow waveform example with PR=0003 RTCCLK RTC_PR 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 RTC_Second RTC_CNT FFFFFFFB FFFFFFFC FFFFFFFD FFFFFFFE FFFFFFFF 0000 RTC_Overflow 1 RTCCLK OWF (not powered in Standby) can be cleared by software Doc ID 13902 Rev 9 391/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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