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Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 238. USART block diagram PWDATA Write (CPU or DMA) Read (CPU or DMA) (DATA REGISTER) DR PRDATA TX Transmit Data Register (TDR) Receive Data Register (RDR) RX SW_RX IrDA SIR ENDEC BLOCK Transmit Shift Register Receive Shift Register IRDA_OUT IRDA_IN GTPR GT CR3 DMAT DMAR SCEN NACK HD IRLP IREN PSC SCLK CONTROL CR2 LINE STOP[1:0] CKEN CPOL CPHA LBCL SCLK CR2 CR1 USART Address UE M WAKE PCE PS PEIE nRTS nCTS Hardware flow controller TRANSMIT CONTROL WAKE UP UNIT RECEIVER CONTROL RECEIVER CLOCK CR1 TXEIE TCIE RXNE IDLE IE IE TE RE RWU SBK CTS LBD TXETC RXNEIDLEORE NE SR FE PE USART INTERRUPT CONTROL USART_BRR TRANSMITTER CLOCK TE TRANSMITTER RATE CONTROL /16 /USARTDIV f PCLKx(x=1,2) DIV_Mantissa DIV_Fraction 15 4 0 RECEIVER RATE RE CONTROL CONVENTIONAL BAUD RATE GENERATOR USARTDIV = DIV_Mantissa + (DIV_Fraction / 16) 656/995 Doc ID 13902 Rev 9
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 25.3.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 239). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data (The number of “1” ‘s will include the number of stop bits). A Break character is interpreted on receiving “0”s for a frame period. At the end of the break frame the transmitter inserts either 1 or 2 stop bits (logic “1” bit) to acknowledge the start bit. Transmission <strong>and</strong> reception are driven by a common baud rate generator, the clock for each is generated when the enable bit is set respectively for the transmitter <strong>and</strong> receiver. The details of each block is given below. Figure 239. Word length programming Clock 9-bit word length (M bit is set), 1 stop bit Possible Data frame parity bit Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Idle frame ** Stop bit Next Start bit Start bit Next data frame Clock 8-bit word length (M bit is reset), 1 stop bit Start Bit Break frame Data frame Possible Parity Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop Bit Next Start Bit Stop bit Start bit ** LBCL bit controls last data clock pulse **** ** Next data frame Idle frame Break frame Start bit Stop bit Start bit ** LBCL bit controls last data clock pulse Doc ID 13902 Rev 9 657/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) transfe
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RM0008 DMA controller (DMA) not sup
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Debug support (DBG) Note: On
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RM0008 Debug support (DBG) DBGMCU_I
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RM0008 Debug support (DBG) Table 20
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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