STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Debug support (DBG) RM0008 29.2 Reference ARM documentation ● ● ● Cortex-M3 r1p1 Technical Reference Manual (TRM) (see Related documents on page 1) ARM Debug Interface V5 ARM CoreSight Design Kit revision r1p1 Technical Reference Manual 29.3 SWJ debug port (serial wire and JTAG) The STM32F10xxx core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an ARM standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW- DP (2-pin) interface. ● The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP- AP port. ● The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP port. In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP. Figure 321. SWJ debug port TRACESWO (asynchronous trace) SWJ-DP JTDO JTDI JNTRST TDO TDI nTRST TDO TDI nTRST JTAG-DP TCK SWD/JTAG select TMS nPOTRST nPOTRST From power-on reset JTMS/SWDIO SWDITMS SWDO SWDOEN DBGDI DBGDO DBGDOEN DBGRESETn SW-DP JTCK/SWCLK SWCLKTCK DBGCLK Figure 321 shows that the asynchronous TRACE output (TRACESWO) is multiplexed with TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP. 29.3.1 Mechanism to select the JTAG-DP or the SW-DP By default, the JTAG-Debug Port is active. If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG sequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the 954/995 Doc ID 13902 Rev 9
RM0008 Debug support (DBG) JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only the SWCLK and SWDIO pins. This sequence is: 1. Send more than 50 TCK cycles with TMS (SWDIO) =1 2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted first) 3. Send more than 50 TCK cycles with TMS (SWDIO) =1 29.4 Pinout and debug port pins The STM32F10xxx MCU is available in various packages with different numbers of available pins. As a result, some functionality related to pin availability may differ between packages. 29.4.1 SWJ debug port pins Five pins are used as outputs from the STM32F10xxx for the SWJ-DP as alternate functions of General Purpose I/Os. These pins are available on all packages. Table 198. SWJ-DP pin name JTMS/SWDIO SWJ debug port pins JTAG debug port SW debug port Pin assign Type Description Type Debug assignment ment I JTAG Test Mode Selection I/O Serial Wire Data Input/Output PA13 JTCK/SWCLK I JTAG Test Clock I Serial Wire Clock PA14 JTDI I JTAG Test Data Input - - PA15 JTDO/TRACESWO O JTAG Test Data Output - TRACESWO if async trace is enabled PB3 JNTRST I JTAG Test nReset - - PB4 29.4.2 Flexible SWJ-DP pin assignment After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host). However, the STM32F10xxx MCU implements the AF remap and debug I/O configuration register (AFIO_MAPR) register to disable some part or all of the SWJ-DP port and so releases the associated pins for General Purpose I/Os usage. This register is mapped on an APB bridge connected to the Cortex-M3 System Bus. Programming of this register is done by the user software program and not the debugger host. Doc ID 13902 Rev 9 955/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) 18.6
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