STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Bits 6:4 PORT[2:0]: Port selection
Set and cleared by software. Select the port used to output the Cortex EVENTOUT signal.
Note: The EVENTOUT signal output capability is not extended to ports PF and PG.
000: PA selected
001: PB selected
010: PC selected
011: PD selected
100: PE selected
Bits 3:0 PIN[3:0]: Pin selection (x = A .. E)
Set and cleared by software. Select the pin used to output the Cortex EVENTOUT signal.
0000: Px0 selected
0001: Px1 selected
0010: Px2 selected
0011: Px3 selected
...
1111: Px15 selected
8.4.2 AF remap and debug I/O configuration register (AFIO_MAPR)
Address offset: 0x04
Reset value: 0x0000 0000
Memory map and bit definitions for low-, medium- and high-density devices:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
SWJ_
CFG[2:0]
Reserved
ADC2_
ETRGR
EG_RE
MAP
ADC2_
ETRGIN
J_REM
AP
ADC1_
ETRGR
EG_RE
MAP
ADC1_
ETRGIN
J_REM
AP
w w w rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD01_
REMAP
CAN_REMAP
[1:0]
TIM4_
REMAP
TIM3_REMAP
[1:0]
TIM2_REMAP
[1:0]
TIM1_REMAP
[1:0]
USART3_
REMAP[1:0]
USART
2_
REMAP
USART
1_
REMAP
I2C1_
REMAP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
TIM5CH
4_IREM
AP
SPI1_
REMAP
Bits 31:27
Reserved
Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration
These bits are write-only (when read, the value is undefined). They are used to configure the
SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD
access to the Cortex debug port. The default state after reset is SWJ ON without trace. This
allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /
JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: no effect
Bits 23:21
Reserved
Doc ID 13902 Rev 9 159/995