STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

USB on-the-go full-speed (OTG_FS)
RM0008
Table 182.
Acronym
Host-mode control and status registers (CSRs) (continued)
Offset
address
Register name
OTG_FS_HCCHARx
OTG_FS_HCINTx
OTG_FS_HCINTMSKx
OTG_FS_HCTSIZx
0x500
0x520
...
0x6E0h
508h
50Ch
510h
OTG_FS host channel-x characteristics register (OTG_FS_HCCHARx)
(x = 0..7, where x = Channel_number) on page 751
OTG_FS host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7,
where x = Channel_number) on page 752
OTG_FS host channel-x interrupt mask register (OTG_FS_HCINTMSKx)
(x = 0..7, where x = Channel_number) on page 753
OTG_FS host channel-x transfer size register (OTG_FS_HCTSIZx)
(x = 0..7, where x = Channel_number) on page 754
Device-mode CSR map
These registers must be programmed every time the core changes to Device mode.
Table 183.
Acronym
Device-mode control and status registers
Offset
address
Register name
OTG_FS_DCFG 0x800 OTG_FS device configuration register (OTG_FS_DCFG) on page 755
OTG_FS_DCTL 0x804 OTG_FS device control register (OTG_FS_DCTL) on page 756
OTG_FS_DSTS 0x808 OTG_FS device status register (OTG_FS_DSTS) on page 757
OTG_FS_DIEPMSK
OTG_FS_DOEPMSK
OTG_FS_DAINT
OTG_FS_DAINTMSK
OTG_FS_DVBUSDIS
OTG_FS_DVBUSPULSE
OTG_FS_DIEPEMPMSK
OTG_FS_DIEPCTL0
0x810
0x814
0x818
0x81C
0x828
0x82C
0x834
0x900
OTG_FS device IN endpoint common interrupt mask register
(OTG_FS_DIEPMSK) on page 758
OTG_FS device OUT endpoint common interrupt mask register
(OTG_FS_DOEPMSK) on page 759
OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) on
page 760
OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
on page 761
OTG_FS device V BUS discharge time register (OTG_FS_DVBUSDIS)
on page 761
OTG_FS device V BUS pulsing time register (OTG_FS_DVBUSPULSE)
on page 762
OTG_FS device IN endpoint FIFO empty interrupt mask register:
(OTG_FS_DIEPEMPMSK) on page 762
OTG_FS device control IN endpoint 0 control register
(OTG_FS_DIEPCTL0) on page 763
720/995 Doc ID 13902 Rev 9