STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Revision history
Table 215.
Document revision history (continued)
Date Revision Changes
23-Dec-2008 7
Memory map figure removed from reference manual. Section 2.1: System
architecture on page 38 modified. Section 2.4: Boot configuration on
page 48 modified. Exiting Sleep mode on page 58 modified. Section 5.3.2:
RTC calibration on page 67 updated. Wakeup event management on
page 175 updated.
Section 6.3: RCC registers on page 82 updated. Section 10.2: DMA main
features on page 182 updated.
Section 10.3.5: Error management modified. Figure 22: DMA block diagram
in connectivity line devices on page 183 modified. Section 10.3.4:
Programmable data width, data alignment and endians on page 186 added.
Bit definition modified in Section 10.4.5: DMA channel x peripheral address
register (DMA_CPARx) (x = 1 ..7) on page 195 and Section 10.4.6: DMA
channel x memory address register (DMA_CMARx) (x = 1 ..7) on page 195.
Note added below Figure 81: PWM input mode timing and Figure 127: PWM
input mode timing.
FSMC_NWAIT signal direction corrected in Figure 19.3: AHB interface on
page 410.
Value to set modified for bit 6 in Table 98: FSMC_BCRx bit fields, Table 101:
FSMC_BCRx bit fields and Table 107: FSMC_BCRx bit fields. Table 114: 8-
bit NAND Flash, Table 115: 16-bit NAND Flash and Table 116: 16-bit PC
Card modified. NWAIT and INTR signals separated in Table 116: 16-bit PC
Card. Note added in PWAITEN bit definition in PC Card/NAND Flash control
registers 2..4 (FSMC_PCR2..4) on page 448.
Bit definitions updated in FIFO status and interrupt register 2..4
(FSMC_SR2..4) on page 449. Note modified in ADDHLD and ADDSET bit
definitions in SRAM/NOR-Flash chip-select timing registers 1..4
(FSMC_BTR1..4) on page 438. Bit 8 is reserved in PC Card/NAND Flash
control registers 2..4 (FSMC_PCR2..4) on page 448.
MEMWAIT[15:8] bit definition modified in Common memory space timing
register 2..4 (FSMC_PMEM2..4) on page 450.
ATTWAIT[15:8] bit definition modified in Attribute memory space timing
registers 2..4 (FSMC_PATT2..4) on page 451.
Section 19.6.5: NAND Flash pre-wait functionality on page 446 modified.
Figure 175: NAND/PC Card controller timing for common memory access
modified.
Note added below Table 84: NOR/PSRAM bank selection on page 412.
32-bit external memory access removed from Table 85: External memory
address on page 412 and note added.
Caution: added to Section 19.6.1: External memory interface signals on
page 442.
NIOS16 description modified in Table 116: 16-bit PC Card on page 443.
Register description modified in Attribute memory space timing registers 2..4
(FSMC_PATT2..4) on page 451.
Resetting the password on page 478 step 2 corrected.
write_data signal modified in Figure 175: NAND/PC Card controller timing
for common memory access.
bxCAN main features on page 542 modified.
Section 24.3.8: Packet error checking on page 639 modified.
Section 29.6.3: Cortex-M3 TAP modified.
DBG_TIMx_STOP positions modified in DBGMCU_CR on page 972.
Small text changes.
Doc ID 13902 Rev 9 989/995