STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Analog-to-digital converter (ADC) RM0008 Figure 25. Single ADC block diagram End of conversion Flags EOC End of injected conversion JEOC Analog watchdog event AWD Interrupt enable bits EOCIE JEOCIE AWDIE ADC Interrupt to NVIC Analog watchdog Compare Result High Threshold (12 bits) Low Threshold (12 bits) ADCx_IN0 V REF+ V REF- V DDA V SSA Analog MUX Injected data registers (4 x 16 bits) Regular data register (16 bits) DMA request Address/data bus ADCx_IN1 ADCx_IN15 GPIO Ports up to 4 up to 16 Injected channels Regular channels Analog to digital converter ADCCLK Temp. sensor V REFINT JEXTSEL[2:0] bits From ADC prescaler TIM1_TRGO TIM1_CH4 TIM2_TRGO TIM2_CH1 TIM3_CH4 TIM4_TRGO JEXTRIG bit Start trigger (injected group) EXTI_15 TIM8_CH4 (2) JEXTSEL[2:0] bits EXTI_11 ADCx-ETRGINJ_REMAP bit TIM1_CH1 TIM1_CH2 TIM1_CH3 TIM2_CH2 TIM3_TRGO TIM4_CH4 TIM8_TRGO (2) EXTSEL[2:0] bits Start trigger (regular group) EXTRIG bit TIM1_TRGO TIM1_CH4 TIM4_CH3 TIM8_CH2 TIM8_CH4 TIM5_TRGO TIM5_CH4 TIM3_CH1 TIM2_CH3 TIM1_CH3 TIM8_CH1 TIM8_TRGO TIM5_CH1 TIM5_CH3 JEXTRIG bit Start trigger (injected group) EXTSEL[2:0] bits EXTRIG bit Start trigger (regular group) ADCx_ETRGREG_REMAP bit Triggers for ADC3 (1) ai14802d 1. ADC3 has regular and injected conversion triggers different from those of ADC1 and ADC2. 2. TIM8_CH4 and TIM8_TRGO with their corresponding remap bits exist only in High-density products. 200/995 Doc ID 13902 Rev 9
RM0008 Analog-to-digital converter (ADC) Table 60. ADC pins Name Signal type Remarks V REF+ V DDA V REF- V SSA Input, analog reference positive Input, analog supply Input, analog reference negative Input, analog supply ground The higher/positive reference voltage for the ADC, 2.4 V V REF+ V DDA Analog power supply equal to V DD and 2.4 V V DDA V DD (3.6 V) The lower/negative reference voltage for the ADC, V REF- = V SSA Ground for analog power supply equal to V SS ADCx_IN[15:0] Analog input signals 16 analog input channels 11.3.1 ADC on-off control The ADC can be powered-on by setting the ADON bit in the ADC_CR2 register. When the ADON bit is set for the first time, it wakes up the ADC from Power Down mode. Conversion starts when ADON bit is set for a second time by software after ADC power-up time (t STAB ). You can stop conversion and put the ADC in power down mode by resetting the ADON bit. In this mode the ADC consumes almost no power (only a few µA). 11.3.2 ADC clock The ADCCLK clock provided by the Clock Controller is synchronous with the PCLK2 (APB2 clock). The RCC controller has a dedicated programmable prescaler for the ADC clock, refer to Low-, medium- and high-density reset and clock control (RCC) on page 74 for more details. 11.3.3 Channel selection There are 16 multiplexed channels. It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions which can be done on any channel and in any order. For instance, it is possible to do the conversion in the following order: Ch3, Ch8, Ch2, Ch2, Ch0, Ch2, Ch2, Ch15. ● The regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRx registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the ADC_SQR1 register. ● The injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register. The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the new chosen group. Doc ID 13902 Rev 9 201/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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