STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Low-, medium- and high-density reset and clock control (RCC)
Figure 8.
Clock tree
USB
Prescaler
/1, 1.5
48 MHz
USBCLK
to USB interface
I2S3CLK
to I2S3
OSC_OUT
OSC_IN
OSC32_IN
OSC32_OUT
8 MHz
HSI RC
PLLSRC
PLLMUL
SW
..., x16
HSI
SYSCLK AHB
x2, x3, x4
Prescaler
PLLCLK 72 MHz
PLL
max /1, 2..512
HSE
4-16 MHz
HSE OSC
LSE OSC
32.768 kHz
LSI RC
40 kHz
HSI
PLLXTPRE
/2
/128
/2
LSE
RTCSEL[1:0]
LSI
RTCCLK
CSS
to RTC
to Independent Watchdog (IWDG)
IWDGCLK
Peripheral clock
enable
Peripheral clock
enable
72 MHz max
/8
Clock
Enable
APB1
Prescaler
/1, 2, 4, 8, 16
HCLK
to AHB bus, core,
memory and DMA
Peripheral Clock
Enable
PCLK1
to APB1
peripherals
TIM2,3,4,5,6,7
If (APB1 prescaler =1) x1 to TIM2,3,4,5,6 and 7
else x2 TIMXCLK
Peripheral Clock
Enable
APB2
Prescaler
/1, 2, 4, 8, 16
36 MHz max
72 MHz max
to Cortex System timer
FCLK Cortex
free running clock
Peripheral Clock
Enable
PCLK2
peripherals to APB2
TIM1 & 8 timers
to TIM1 and TIM8
If (APB2 prescaler =1) x1
else x2 TIMxCLK
Peripheral Clock
Enable
ADC
to ADC1, 2 or 3
Prescaler
ADCCLK 14 MHz max
/2, 4, 6, 8
/2
I2S2CLK
Peripheral clock
enable
Peripheral clock
enable
to I2S2
SDIOCLK
FSMCCLK
HCLK/2
to SDIO
to FSMC
To SDIO AHB interface
Peripheral clock
enable
MCO
Main
Clock Output
MCO
/2 PLLCLK
HSI
HSE
SYSCLK
Legend:
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
LSE = Low -speed external clock signal
ai14752d
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For full details about the internal and external clock source characteristics, please refer to the “Electrical
characteristics” section in your device datasheet.
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2.
The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by
the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The timer clock frequencies are automatically fixed by hardware. There are two cases:
Doc ID 13902 Rev 9 77/995