STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Revision history
RM0008
Table 215.
22-May-2008
continued
Document revision history (continued)
Date Revision Changes
4
continued
Figure 205: CAN frames on page 560 modified. Bits 31:21 and bits 20:3
modified in CAN TX mailbox identifier register (CAN_TIxR) (x=0..2) on
page 573. Bits 31:21 and bits 20:3 modified in CAN receive FIFO mailbox
identifier register (CAN_RIxR) (x=0..1) on page 576.
Section 24.3.7: DMA requests on page 637 modified. DMAEN bit 11
description modified in Section 24.6.2: Control register 2 (I2C_CR2) on
page 643.
Clock phase and clock polarity on page 591 modified. Transmit sequence on
page 593 modified. Receive sequence on page 594 added. Reception
sequence on page 612 modified. Underrun flag (UDR) on page 613
modified.
I 2 S feature added (see Section 23: Serial peripheral interface (SPI) on
page 586).
In Section 29: Debug support (DBG) on page 952:
– DBGMCU_IDCODE on page 959 and DBGMCU_CR on page 972
updated
– TMC TAP changed to boundary scan TAP
– Address onto which DBGMCU_CR is mapped modified in
Section 29.16.3: Debug MCU configuration register on page 972.
Section 28: Device electronic signature on page 949 added.
REV_ID(15:0) definition modified in Section 29.6.1: MCU device ID code on
page 958.
986/995 Doc ID 13902 Rev 9