STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Flexible static memory controller (FSMC)
Table 111.
FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-20 0x0000
19 CBURSTRW 0x1
18-15 0x0
14 EXTMOD 0x0
13 WAITEN
12 WREN no effect on synchronous read
11 WAITCFG 0x0
10 WRAPMOD to be set according to memory
9 WAITPOL to be set according to memory
8 BURSTEN no effect on synchronous write
When high, the first data after latency period is taken as always
valid, regardless of the wait from memory value
7 FWPRLVL Set to protect memory from accidental writes
6 FACCEN Set according to memory support
5-4 MWID As needed
3-2 MTYP 0x1
1 MUXEN As needed
0 MBKEN 0x1
Table 112.
FSMC_TCRx bit fields
Bit No. Bit name Value to set
31-30 - 0x0
27-24 DATLAT Data latency
23-20 CLKDIV
19-16 BUSTURN No effect
15-8 DATAST No effect
7-4 ADDHLD No effect
3-0 ADDSET No effect
0 to get CLK = HCLK (not supported)
1 to get CLK = 2 × HCLK
Doc ID 13902 Rev 9 435/995