STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Serial peripheral interface (SPI)
Figure 211. I 2 S block diagram
Address and data bus
Tx buffer
16-bit
BSY OVR MODF CRC
ERR
UDR
CH
TxE RxNE
SIDE
MOSI/ SD
MISO
Shift register
16-bit
Rx buffer
LSB first
Communication
control
NSS/WS
I2SCFG I2SSTD CKPOL DATLEN
[1:0] [1:0] [1:0]
CH
LEN
I2S
MOD I2SE
Master control logic
SPI
baud rate generator
Bidi
mode Bidi
OE
CRC CRC
EN Next
Rx
DFF SSM SSI
only
LSB
First
SPE BR2 BR1 BR0 MSTR CPOL CPHA
CK
I2S_CK
I 2 S clock generator
I2SMOD
MCK
MCKOE ODD I2SDIV[7:0]
I2SxCLK
ai14748
The SPI could function as an audio I 2 S interface when the I 2 S capability is enabled (by
setting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same
pins, flags and interrupts as the SPI.
The I 2 S shares three common pins with the SPI:
● SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two timemultiplexed
data channels (in simplex mode only).
● WS: Word Select (mapped on the NSS pin) is the data control signal output in master
mode and input in slave mode.
● CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode
and serial clock input in slave mode.
Doc ID 13902 Rev 9 599/995