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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Backup registers (BKP)<br />

RM0008<br />

5 Backup registers (BKP)<br />

Low-density devices are <strong>STM32F101xx</strong>, <strong>STM32F102xx</strong> <strong>and</strong> <strong>STM32F103xx</strong><br />

microcontrollers where the Flash memory density ranges between 16 <strong>and</strong> 32 Kbytes.<br />

Medium-density devices are <strong>STM32F101xx</strong>, <strong>STM32F102xx</strong> <strong>and</strong> <strong>STM32F103xx</strong><br />

microcontrollers where the Flash memory density ranges between 64 <strong>and</strong> 128 Kbytes.<br />

High-density devices are <strong>STM32F101xx</strong> <strong>and</strong> <strong>STM32F103xx</strong> microcontrollers where the<br />

Flash memory density ranges between 256 <strong>and</strong> 512 Kbytes.<br />

Connectivity line devices are <strong>STM32F105xx</strong> <strong>and</strong> STM32F107xx microcontrollers.<br />

This Section applies to the whole STM32F10xxx family, unless otherwise specified.<br />

5.1 BKP introduction<br />

The backup registers are forty two 16-bit registers for storing 84 bytes of user application<br />

data. They are implemented in the backup domain that remains powered on by V BAT when<br />

the V DD power is switched off. They are not reset when the device wakes up from St<strong>and</strong>by<br />

mode or by a system reset or power reset.<br />

In addition, the BKP control registers are used to manage the Tamper detection feature <strong>and</strong><br />

RTC calibration.<br />

After reset, access to the Backup registers <strong>and</strong> RTC is disabled <strong>and</strong> the Backup domain<br />

(BKP) is protected against possible parasitic write access. To enable access to the Backup<br />

registers <strong>and</strong> the RTC, proceed as follows:<br />

● enable the power <strong>and</strong> backup interface clocks by setting the PWREN <strong>and</strong> BKPEN bits<br />

in the RCC_APB1ENR register<br />

● set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup<br />

registers <strong>and</strong> RTC.<br />

5.2 BKP main features<br />

●<br />

●<br />

●<br />

●<br />

20-byte data registers (in medium-density <strong>and</strong> low-density devices) or 84-byte data<br />

registers (in high-density <strong>and</strong> connectivity line devices)<br />

Status/control register for managing tamper detection with interrupt capability<br />

Calibration register for storing the RTC calibration value<br />

Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on<br />

TAMPER pin PC13 (when this pin is not used for tamper detection)<br />

66/995 Doc ID 13902 Rev 9

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