STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

USB on-the-go full-speed (OTG_FS)
RM0008
● Application requirements
1. To receive a SETUP packet, the STUPCNT field (OTG_FS_DOEPTSIZx) in a control
OUT endpoint must be programmed to a non-zero value. When the application
programs the STUPCNT field to a non-zero value, the core receives SETUP packets
and writes them to the receive FIFO, irrespective of the NAK status and EPENA bit
setting in OTG_FS_DOEPCTLx. The STUPCNT field is decremented every time the
control endpoint receives a SETUP packet. If the STUPCNT field is not programmed to
a proper value before receiving a SETUP packet, the core still receives the SETUP
packet and decrements the STUPCNT field, but the application may not be able to
determine the correct number of SETUP packets received in the Setup stage of a
control transfer.
– STUPCNT = 3 in OTG_FS_DOEPTSIZx
2. The application must always allocate some extra space in the Receive data FIFO, to be
able to receive up to three SETUP packets on a control endpoint.
– The space to be reserved is 10 DWORDs. Three DWORDs are required for the
first SETUP packet, 1 DWORD is required for the Setup stage done DWORD and
6 DWORDs are required to store two extra SETUP packets among all control
endpoints.
– 3 DWORDs per SETUP packet are required to store 8 bytes of SETUP data and 4
bytes of SETUP status (Setup packet pattern). The core reserves this space in the
receive data.
– FIFO to write SETUP data only, and never uses this space for data packets.
3. The application must read the 2 DWORDs of the SETUP packet from the receive FIFO.
4. The application must read and discard the Setup stage done DWORD from the receive
FIFO.
● Internal data flow
5. When a SETUP packet is received, the core writes the received data to the receive
FIFO, without checking for available space in the receive FIFO and irrespective of the
endpoint’s NAK and STALL bit settings.
– The core internally sets the IN NAK and OUT NAK bits for the control IN/OUT
endpoints on which the SETUP packet was received.
6. For every SETUP packet received on the USB, 3 DWORDs of data are written to the
receive FIFO, and the STUPCNT field is decremented by 1.
– The first DWORD contains control information used internally by the core
– The second DWORD contains the first 4 bytes of the SETUP command
– The third DWORD contains the last 4 bytes of the SETUP command
7. When the Setup stage changes to a Data IN/OUT stage, the core writes an entry
(Setup stage done DWORD) to the receive FIFO, indicating the completion of the Setup
stage.
8. On the AHB side, SETUP packets are emptied by the application.
9. When the application pops the Setup stage done DWORD from the receive FIFO, the
core interrupts the application with an STUP interrupt (OTG_FS_DOEPINTx),
indicating it can process the received SETUP packet.
– The core clears the endpoint enable bit for control OUT endpoints.
814/995 Doc ID 13902 Rev 9