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Analog-to-digital converter (ADC) RM0008 Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence These bits are written by software with the channel number (0..17) assigned as the 4th in the sequence to be converted. Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels are converted in a sequence starting from (4-JL). Example: ADC_JSQR[21:0] = 10 00011 00011 00111 00010 means that a scan conversion will convert the following channel sequence: 7, 3, 3. (not 2, 7, 3) Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence 11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) Address offset: 0x3C - 0x48 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JDATA[15:0] r r r r r r r r r r r r r r r r Bits 31:16 Reserved, must be kept cleared. Bits 15:0 JDATA[15:0]: Injected data These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in Figure 30 and Figure 31. 11.12.14 ADC regular data register (ADC_DR) Address offset: 0x4C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADC2DATA[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA[15:0] r r r r r r r r r r r r r r r r Bits 31:16 ADC2DATA[15:0]: ADC2 data – In ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to Section 11.9: Dual ADC mode – In ADC2 and ADC3: these bits are not used Bits 15:0 DATA[15:0]: Regular data These bits are read only. They contain the conversion result from the regular channels. The data is left or right-aligned as shown in Figure 30 and Figure 31. 230/995 Doc ID 13902 Rev 9
RM0008 Analog-to-digital converter (ADC) 11.12.15 ADC register map Table 67. Offset The following table summarizes the ADC registers. ADC register map and reset values Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 0x04 0x08 STRT JSTRT JEOC EOC AWD ADC_SR Reserved Reset value 0 0 0 0 0 ADC_CR1 Reserved AWDEN JAWDEN Reserved DUALMOD [3:0] DISC NUM [2:0] JDISCEN DISCEN JAUTO AWD SGL SCAN JEOC IE AWDIE EOCIE AWDCH[4:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_CR2 Reserved TSVREFE SWSTART JSWSTART EXTTRIG EXTSEL [2:0] Reserved JEXTTRIG JEXTSEL [2:0] ALIGN Reserved DMA Reserved RSTCAL CAL CONT ADON Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0C ADC_SMPR1 Sample time bits SMPx_x Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 ADC_SMPR2 Sample time bits SMPx_x Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 ADC_JOFR1 JOFFSET1[11:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 ADC_JOFR2 JOFFSET2[11:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 ADC_JOFR3 JOFFSET3[11:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 ADC_JOFR4 JOFFSET4[11:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 ADC_HTR HT[11:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 ADC_LTR LT[11:0] Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SQR1 L[3:0] Regular channel sequence SQx_x bits Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SQR2 Reserved Regular channel sequence SQx_x bits Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SQR3 Reserved Regular channel sequence SQx_x bits Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_JSQR JL[1:0] Injected channel sequence JSQx_x bits Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Doc ID 13902 Rev 9 231/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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