STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Ethernet (ETH): media access control (MAC) with DMA controller
Figure 312. TxDMA operation in OSF mode
Start TxDMA
Start
Stop TxDMA
(Re-)fetch next
descriptor
Poll
demand
(AHB)
error
No
Yes
TxDMA suspended
Previous frame
status available
No
Own
bit set
Yes
Transfer data from
buffer(s)
Time stamp
present
(AHB)
error
Yes
Yes
No
No
No
Write time stamp to
TDES2 & TDES3
for previous frame
No
Frame xfer
complete
Yes
Second
frame
Yes
Close intermediate
descriptor
Wait for previous
frame’s Tx status
(AHB)
error
No
Yes
Time stamp
present
No
Yes
Write time stamp to
TDES2 & TDES3
for previous frame
Write status word to
prev. frame’s TDES0
Write status word to
prev. frame’s TDES0
No
(AHB)
error
Yes
No
(AHB)
error
No
(AHB)
error
Yes
Yes
ai15640
Transmit frame processing
The transmit DMA expects that the data buffers contain complete Ethernet frames,
excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain
valid data. If the transmit descriptor indicates that the MAC core must disable CRC or pad
insertion, the buffer must have complete Ethernet frames (excluding preamble), including
the CRC bytes. Frames can be data-chained and span over several buffers. Frames have to
be delimited by the first descriptor (TDES0[28]) and the last descriptor (TDES0[29]). As the
transmission starts, TDES0[28] has to be set in the first descriptor. When this occurs, the
frame data are transferred from the memory buffer to the Transmit FIFO. Concurrently, if the
last descriptor (TDES0[29]) of the current frame is cleared, the transmit process attempts to
acquire the next descriptor. The transmit process expects TDES0[28] to be cleared in this
descriptor. If TDES0[29] is cleared, it indicates an intermediary buffer. If TDES0[29] is set, it
Doc ID 13902 Rev 9 885/995