STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Revision history
30 Revision history
Table 215.
Document revision history
Date Revision Changes
19-Oct-2007 1
Document reference number changed from UM0306 to RM008. The
changes below were made with reference to revision 1 of 01-Jun-2007 of
UM0306.
EXTSEL[2:0] and JEXTSEL[2:0] removed from Table 60: ADC pins on
page 201 and V REF+ range modified in Remarks column.
Notes added to Section 11.3.9 on page 204, Section 11.9.2 on page 212,
Section 11.9.7 on page 215 and Section 11.9.9 on page 216.
SPI_CR2 corrected to SPI_CR1 in 1 clock and 1 bidirectional data wire on
page 594.
f CPU frequency changed to f PCLK in Section 23.2: SPI and I 2 S main features
on page 587.
Section 23.3.6: CRC calculation on page 595 and Section 23.3.7: SPI
communication using DMA (direct memory addressing) on page 596
modified.
Note added to bit 13 description changed in Section 23.5.1: SPI control
register 1 (SPI_CR1) (not used in I 2 S mode) on page 614. Note for bit 4
modified in Section 23.5.3: SPI status register (SPI_SR) on page 617.
On 64-pin packages on page 54 modified.
Section 8.3.2: Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 on
page 152 updated.
Description of SRAM at address 0x4000 6000 modified in Figure 2: Memory
map on page 39 and Table 1: Register boundary addresses.
Note added to Section 21.2: USB main features on page 512 and
Section 22.2: bxCAN main features on page 542.
Figure 4: Power supply overview and On 100-pin and 144- pin packages
modified.
Formula added to Bits 25:24 description in CAN bit timing register
(CAN_BTR) on page 571.
Section 10.3: DMA functional description on page 183 modified.
Example of configuration on page 970 modified.
MODEx[1:0] bit definitions corrected in Section 8.2.2: Port configuration
register high (GPIOx_CRH) (x=A..G) on page 149.
Downcounting mode on page 260 modified.
Figure 80: Output stage of capture/compare channel (channel 4) on
page 271 and Figure 82: Output compare mode, toggle on OC1. modified.
OCx output enable conditions modified in Section 13.3.10: PWM mode on
page 275.
Section 13.3.19: TIMx and external trigger synchronization on page 290 title
changed.
CC1S, CC2S, CC3S and CC4S definitions modified for (1, 1) bit setting
modified in Section 13.4.7: TIM1&TIM8 capture/compare mode register 1
(TIMx_CCMR1) and Section 13.4.8: TIM1&TIM8 capture/compare mode
register 2 (TIMx_CCMR2).
CC1S, CC2S, CC3S and CC4S definitions for (1, 1) bit setting modified in
Section 14.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1) and
Section 14.4.8: Capture/compare mode register 2 (TIMx_CCMR2).
AFIO_EVCR pins modified in Table 51: AFIO register map and reset values
on page 167. Section 13.3.6: Input capture mode on page 271 modified.
Doc ID 13902 Rev 9 981/995