STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Ethernet (ETH): media access control (MAC) with DMA controller
RM0008
27.3 Ethernet pins and internal signals
Table 188.
Table 188 shows the MAC signals and the corresponding MII/RMII default or remapped
signals. It also indicates the pins onto which the signals are input or output, and the pin
configuration.
Ethernet pin configuration
MAC signals MII default MII remap RMII default RMII remap Pin Pin configuration
ETH_MDC MDC - MDC - PC1
ETH_MII_TXD2 TXD2 - - - PC2
AF output push-pull highspeed
(50 MHz)
AF output push-pull highspeed
(50 MHz)
ETH_MII_TX_CLK TX_CLK - - - PC3 Floating input (reset state)
ETH_MII_CRS CRS - - - PA0 Floating input (reset state)
ETH_MII_RX_CLK
ETH_RMII_REF_CLK
RX_CLK - REF_CLK - PA1 Floating input (reset state)
ETH_MDIO MDIO - MDIO - PA2
AF output push-pull highspeed
(50 MHz)
ETH_MII_COL COL - - - PA3 Floating input (reset state)
ETH_MII_RX_DV
ETH_RMII_CRS_DV
RX_DV - CRS_DV - PA7 Floating input (reset state)
ETH_MII_RXD0
ETH_RMII_RXD0
RXD0 - RXD0 - PC4 Floating input (reset state)
ETH_MII_RXD1
ETH_RMII_RXD1
RXD1 - RXD1 - PC5 Floating input (reset state)
ETH_MII_RXD2 RXD2 - - - PB0 Floating input (reset state)
ETH_MII_RXD3 RXD3 - - - PB1 Floating input (reset state)
ETH_MII_RX_ER RX_ER - - - PB10 Floating input (reset state)
ETH_MII_TX_EN
ETH_RMII_TX_EN
ETH_MII_TXD0
ETH_RMII_TXD0
ETH_MII_TXD1
ETH_RMII_TXD1
TX_EN - TX_EN - PB11
TXD0 - TXD0 - PB12
TXD1 - TXD1 - PB13
ETH_PPS_OUT PPS_OUT - PPS_OUT - PB5
ETH_MII_TXD3 TXD3 - - - PB8
AF output push-pull highspeed
(50 MHz)
AF output push-pull highspeed
(50 MHz)
AF output push-pull highspeed
(50 MHz)
AF output push-pull highspeed
(50 MHz)
AF output push-pull highspeed
(50 MHz)
ETH_RMII_CRS_DV - RX_DV - CRS_DV PD8 Floating input (reset state)
ETH_MII_RXD0
ETH_RMII_RXD0
ETH_MII_RXD1
ETH_RMII_RXD1
- RXD0 - RXD0 PD9 Floating input (reset state)
- RXD1 - RXD1 PD10 Floating input (reset state)
840/995 Doc ID 13902 Rev 9