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DMA controller (DMA) RM0008 Figure 24. DMA2 request mapping Peripheral request signals Fixed hardware priority TIM5_CH4 TIM5_TRIG TIM8_CH3 TIM8_UP SPI/I2S3_RX TIM8_CH4 TIM8_TRIG TIM8_COM TIM5_CH3 TIM5_UP SPI/I2S3_TX HW request 1 Channel 1 SW trigger (MEM2MEM bit) Channel 1 EN bit HW request 2 Channel 2 SW trigger (MEM2MEM bit) Channel 2 EN bit HIGH PRIORITY TIM8_CH1 UART4_RX TIM6_UP/DAC_Channel1 TIM5_CH2 SDIO TIM7_UP/DAC_Channel2 HW request 3 Channel 3 SW trigger (MEM2MEM bit) Channel 3 EN bit HW request 4 Channel 4 SW trigger (MEM2MEM bit) internal DMA2 request Channel 4 EN bit ADC3 TIM8_CH2 TIM5_CH1 UART4_TX HW request 5 SW trigger (MEM2MEM bit) Channel 5 LOW PRIORITY Channel 5 EN bit Table 58 lists the DMA2 requests for each channel. Table 58. Summary of DMA2 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 ADC3 (1) SPI/I2S3 SPI/I2S3_RX SPI/I2S3_TX 1. ADC3, SDIO <strong>and</strong> TIM8 DMA requests are available only in high-density devices. ADC3 UART4 UART4_RX UART4_TX SDIO (1) SDIO TIM5 TIM6/ DAC_Channel1 TIM7/ DAC_Channel2 TIM8 (1) TIM5_CH4 TIM5_TRIG TIM8_CH3 TIM8_UP TIM5_CH3 TIM5_UP TIM8_CH4 TIM8_TRIG TIM8_COM TIM6_UP/ DAC_Channel1 TIM5_CH2 TIM7_UP/ DAC_Channel2 TIM5_CH1 TIM8_CH1 TIM8_CH2 190/995 Doc ID 13902 Rev 9
RM0008 DMA controller (DMA) 10.4 DMA registers Note: Refer to Section 1.1 on page 37 for a list of abbreviations used in the register descriptions. In the following registers, all bits relative to channel6 <strong>and</strong> channel7 are not relevant for DMA2 since it has only 5 channels. 10.4.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5 r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 r r r r r r r r r r r r r r r r Bits 31:28 Reserved, always read as 0. Bits 27, 23, 19, 15, 11, 7, 3 Bits 26, 22, 18, 14, 10, 6, 2 Bits 25, 21, 17, 13, 9, 5, 1 Bits 24, 20, 16, 12, 8, 4, 0 TEIFx: Channel x transfer error flag (x = 1 ..7) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel x 1: A transfer error (TE) occurred on channel x HTIFx: Channel x half transfer flag (x = 1 ..7) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel x 1: A half transfer (HT) event occurred on channel x TCIFx: Channel x transfer complete flag (x = 1 ..7) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel x 1: A transfer complete (TC) event occurred on channel x GIFx: Channel x global interrupt flag (x = 1 ..7) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel x 1: A TE, HT or TC event occurred on channel x Doc ID 13902 Rev 9 191/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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