STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Ethernet (ETH): media access control (MAC) with DMA controller
RM0008
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RDES0: Receive descriptor Word0
Refer to RDES0: Receive descriptor Word0 section
RDES1: Receive descriptor Word1
Refer to RDES1: Receive descriptor Word1 section
RDES2: Receive descriptor Word2
The table below describes the fields that have different meaning for RDES2 when the
receive descriptor is closed and time stamping is enabled.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTSL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
.
Bits 31:0 RTSL: Receive frame time stamp low
The DMA updates this field with the 32 least significant bits of the time stamp captured for the
corresponding receive frame. The DMA updates this field only for the last descriptor of the receive
frame indicated by last descriptor status bit (RDES0[8]). When this field and the RTSH field in RDES3
show all ones, the time stamp must be treated as corrupt.
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RDES3: Receive descriptor Word3
The table below describes the fields that have different meaning for RDES3 when the
receive descriptor is closed and time stamping is enabled.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTSH
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
.
Bits 31:0 RTSH: Receive frame time stamp high
The DMA updates this field with the 32 most significant bits of the time stamp captured for the
corresponding receive frame. The DMA updates this field only for the last descriptor of the receive frame
indicated by last descriptor status bit (RDES0[8]).
When this field and RDES2’s RTSL field show all ones, the time stamp must be treated as
corrupt.
27.6.9 DMA interrupts
Interrupts can be generated as a result of various events. The ETH_DMASR register
contains all the bits that might cause an interrupt. The ETH_DMAIER register contains an
enable bit for each of the events that can cause an interrupt.
There are two groups of interrupts, Normal and Abnormal, as described in the
ETH_DMASR register. Interrupts are cleared by writing a 1 to the corresponding bit position.
When all the enabled interrupts within a group are cleared, the corresponding summary bit
is cleared. If the MAC core is the cause for assertion of the interrupt, then any of the TSTS
or PMTS bits in the ETH_DMASR register is set high.
Interrupts are not queued and if the interrupt event occurs before the driver has responded
to it, no additional interrupts are generated. For example, the Receive Interrupt bit
(ETH_DMASR register [6]) indicates that one or more frames were transferred to the
904/995 Doc ID 13902 Rev 9