STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Revision history
RM0008
Table 215.
Document revision history (continued)
Date Revision Changes
26-Sep-2008 6
This reference manual also applies to low-density STM32F101xx,
STM32F102xx and STM32F103xx devices, and to medium-density
STM32F102xx devices. In all sections, definitions of low-density and
medium-density devices updated.
Section 1.3: Peripheral availability on page 37 added.
Section 2.3.3: Embedded Flash memory on page 44 updated. Section 4.1.2:
Battery backup domain on page 54 modified. Reset value of Port input data
register (GPIOx_IDR) (x=A..G) on page 149 modified. Note added in
Section 8.4: AFIO registers on page 158. Note removed from bits 18:0
description in Section 9.3.6: Pending register (EXTI_PR) on page 180.
Section 13.2: TIM1&TIM8 main features on page 253 and Section 14.2:
TIMx main features on page 320 updated. In Section 14.3.15: Timer
synchronization on page 349, TS=000.
FSMC_CLK signal direction corrected in Figure 19.3: AHB interface on
page 410. “Feedback clock” paragraph removed from Section 19.5.3:
General timing rules on page 417.
In Section 19.5.6: NOR/PSRAM controller registers on page 436: reset
value modified, WAITEN bit default value after reset is 1, bits [5:6] definition
modified, , FACCEN default value after reset specified. NWE signal behavior
corrected in Figure 174: Synchronous multiplexed write mode - PSRAM
(CRAM) on page 434. The FSMC interface does not support COSMO RAM
and OneNAND devices, and it does not support the asynchronous wait
feature. SRAM and ROM 32 memory data size removed from Table 92: NOR
Flash/PSRAM supported memories and transactions on page 416.
Data latency versus NOR Flash latency on page 431 modified. Bits 19:16
bits are reserved in SRAM/NOR-Flash write timing registers 1..4
(FSMC_BWTR1..4) on page 440.
Section 19.6.3: Timing diagrams for NAND, ATA and PC Card on page 444
modified.Definition of PWID bits modified in Section 19.6.7: NAND Flash/PC
Card controller registers on page 448. Section 19.6.6: Error correction code
computation ECC (NAND Flash) on page 447 modified.
Interrupt Mapper definition modified in Section 21.3.1: Description of USB
blocks on page 514. USB register and memory base addresses modified in
Section 21.5: USB registers on page 526.
Section 24.3.8: Packet error checking on page 639 modified.
Section : Start bit detection on page 661 added. PE bit description specified
in Status register (USART_SR) on page 683.
“RAM size register” section removed from Section 28: Device electronic
signature on page 949. Bit definitions updated in FIFO status and interrupt
register 2..4 (FSMC_SR2..4) on page 449.
Small text changes.
988/995 Doc ID 13902 Rev 9