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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Secure digital input/output interface (SDIO)<br />

RM0008<br />

Bit 16 TXFIFOFIE: Tx FIFO full interrupt enable<br />

Set <strong>and</strong> cleared by software to enable/disable interrupt caused by Tx FIFO full.<br />

0: Tx FIFO full interrupt disabled<br />

1: Tx FIFO full interrupt enabled<br />

Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable<br />

Set <strong>and</strong> cleared by software to enable/disable interrupt caused by Rx FIFO half full.<br />

0: Rx FIFO half full interrupt disabled<br />

1: Rx FIFO half full interrupt enabled<br />

Bit 14 TXFIFOHEIE: Tx FIFO half empty interrupt enable<br />

Set <strong>and</strong> cleared by software to enable/disable interrupt caused by Tx FIFO half empty.<br />

0: Tx FIFO half empty interrupt disabled<br />

1: Tx FIFO half empty interrupt enabled<br />

Bit 13 RXACTIE: Data receive acting interrupt enable<br />

Set <strong>and</strong> cleared by software to enable/disable interrupt caused by data being received (data<br />

receive acting).<br />

0: Data receive acting interrupt disabled<br />

1: Data receive acting interrupt enabled<br />

Bit 12 TXACTIE: Data transmit acting interrupt enable<br />

Set <strong>and</strong> cleared by software to enable/disable interrupt caused by data being transferred<br />

(data transmit acting).<br />

0: Data transmit acting interrupt disabled<br />

1: Data transmit acting interrupt enabled<br />

Bit 11 CMDACTIE: Comm<strong>and</strong> acting interrupt enable<br />

Set <strong>and</strong> cleared by software to enable/disable interrupt caused by a comm<strong>and</strong> being<br />

transferred (comm<strong>and</strong> acting).<br />

0: Comm<strong>and</strong> acting interrupt disabled<br />

1: Comm<strong>and</strong> acting interrupt enabled<br />

Bit 10 DBCKENDIE: Data block end interrupt enable<br />

Set <strong>and</strong> cleared by software to enable/disable interrupt caused by data block end.<br />

0: Data block end interrupt disabled<br />

1: Data block end interrupt enabled<br />

Bit 9 STBITERRIE: Start bit error interrupt enable<br />

Set <strong>and</strong> cleared by software to enable/disable interrupt caused by start bit error.<br />

0: Start bit error interrupt disabled<br />

1: Start bit error interrupt enabled<br />

Bit 8 DATAENDIE: Data end interrupt enable<br />

Set <strong>and</strong> cleared by software to enable/disable interrupt caused by data end.<br />

0: Data end interrupt disabled<br />

1: Data end interrupt enabled<br />

Bit 7 CMDSENTIE: Comm<strong>and</strong> sent interrupt enable<br />

Set <strong>and</strong> cleared by software to enable/disable interrupt caused by sending comm<strong>and</strong>.<br />

0: Comm<strong>and</strong> sent interrupt disabled<br />

1: Comm<strong>and</strong> sent interrupt enabled<br />

508/995 Doc ID 13902 Rev 9

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