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General-purpose timer (TIMx) RM0008 14.4.16 TIMx capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR4[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR4[15:0]: Capture/Compare value 1/ if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT <strong>and</strong> signalled on OC4 output. 2/ if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). 14.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBL[4:0] DBA[4:0] Reserved Reserved rw rw rw rw rw rw rw rw rw rw Bits 15:13 Reserved, always read as 0 Bits 12:8 DBL[4:0]: DMA burst length This 5-bits vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of bytes to be transferred. 00000: 1 byte, 00001: 2 bytes, 00010: 3 bytes, ... 10001: 18 bytes. Bits 7:5 Reserved, always read as 0 Bits 4:0 DBA[4:0]: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... 372/995 Doc ID 13902 Rev 9
RM0008 General-purpose timer (TIMx) 14.4.18 TIMx DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAB[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write access to the DMAR register accesses the register located at the address: “(TIMx_CR1 address) + DBA + (DMA index)” in which: TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in the TIMx_DCR register, DMA index is the offset automatically controlled by the DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register. 14.4.19 TIMx register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 78. TIMx register map <strong>and</strong> reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 CKD CMS TIMx_CR1 Reserved [1:0] [1:0] Reset value 0 0 0 0 0 0 0 0 0 0 ARPE DIR OPM URS UDIS CEN TIMx_CR2 MMS[2:0] Reserved Reserved Reset value 0 0 0 0 0 ETPS TIMx_SMCR ETF[3:0] TS[2:0] SMS[2:0] Reserved [1:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_DIER Reserved ETP ECE TDE TI1S MSM CCDS Reserved COMDE CC4DE CC3DE CC2DE CC1DE UDE Reserved TIE Reserved CC4IE CC3IE CC2IE CC1IE UIE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 CC4OF CC3OF CC2OF CC1OF TIMx_SR Reserved Reset value 0 0 0 0 0 0 0 0 0 0 Reserved TIF Reserved CC4IF CC3IF CC2IF CC1IF UIF TG Reserved CC4G CC3G CC2G CC1G UG TIMx_EGR Reserved Reset value 0 0 0 0 0 0 TIMx_CCMR1 OC2M CC2S OC1M CC1S Output Compare Reserved [2:0] [1:0] [2:0] [1:0] mode Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCMR1 IC2 IC1 CC2S CC1S Input Capture IC2F[3:0] PSC IC1F[3:0] PSC Reserved [1:0] [1:0] mode [1:0] [1:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OC2CE OC2PE OC2FE OC1CE OC1PE OC1FE Doc ID 13902 Rev 9 373/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 General-purpose timer (TIMx)
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RM0008 Serial peripheral interface
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RM0008 Universal synchronous asynch
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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