STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Secure digital input/output interface (SDIO)
Figure 186. Command path state machine (CPSM)
On reset
CE-ATA Command
Completion signal
received or
CPSM disabled or
Command CRC failed
Wait_CPL
CPSM Enabled and
pending command
CPSM
disabled
Idle
Response received or
disabled or command
CRC failed
Response Received in CE-ATA
mode and no interrupt and
wait for CE-ATA Command
Completion signal enabled
Pend
Last Data
Enabled and
command start
CPSM disabled or
no response
CPSM Disabled or
command timeout
Receive
Send
Response
started
Wait for response
Wait
Response Received in CE-ATA mode and
no interrupt and wait for CE-ATA
Command Completion signal disabled
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Note:
Note:
When the Wait state is entered, the command timer starts running. If the timeout is reached
before the CPSM moves to the Receive state, the timeout flag is set and the Idle state is
entered.
The command timeout has a fixed value of 64 SDIO_CK clock periods.
If the interrupt bit is set in the command register, the timer is disabled and the CPSM waits
for an interrupt request from one of the cards. If a pending bit is set in the command register,
the CPSM enters the Pend state, and waits for a CmdPend signal from the data path
subunit. When CmdPend is detected, the CPSM moves to the Send state. This enables the
data counter to trigger the stop command transmission.
The CPSM remains in the Idle state for at least eight SDIO_CK periods to meet the N CC and
N RC timing constraints. N CC is the minimum delay between two host commands, and N RC is
the minimum delay between the host command and the card response.
Doc ID 13902 Rev 9 463/995