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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

USB on-the-go full-speed (OTG_FS)<br />

Bit 17 NAKSTS: NAK status<br />

It indicates the following:<br />

0: The core is transmitting non-NAK h<strong>and</strong>shakes based on the FIFO status.<br />

1: The core is transmitting NAK h<strong>and</strong>shakes on this endpoint.<br />

When either the application or the core sets this bit:<br />

For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint,<br />

even if there are data available in the TxFIFO.<br />

For isochronous IN endpoints: The core sends out a zero-length data packet, even if there<br />

are data available in the TxFIFO.<br />

Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK<br />

h<strong>and</strong>shake.<br />

Bit 16 EONUM: Even/odd frame<br />

Applies to isochronous IN endpoints only.<br />

Indicates the frame number in which the core transmits/receives isochronous data for this<br />

endpoint. The application must program the even/odd frame number in which it intends to<br />

transmit/receive isochronous data for this endpoint using the SEVNFRM <strong>and</strong> SODDFRM<br />

fields in this register.<br />

0: Even frame<br />

1: Odd frame<br />

DPID: Endpoint data PID<br />

Applies to interrupt/bulk IN endpoints only.<br />

Contains the PID of the packet to be received or transmitted on this endpoint. The<br />

application must program the PID of the first packet to be received or transmitted on this<br />

endpoint, after the endpoint is activated. The application uses the SD0PID register field to<br />

program either DATA0 or DATA1 PID.<br />

0: DATA0<br />

1: DATA1<br />

Bit 15 USBAEP: USB active endpoint<br />

Indicates whether this endpoint is active in the current configuration <strong>and</strong> interface. The core<br />

clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving<br />

the SetConfiguration <strong>and</strong> SetInterface comm<strong>and</strong>s, the application must program endpoint<br />

registers accordingly <strong>and</strong> set this bit.<br />

Bits 14:11 Reserved<br />

Bits 10:0 MPSIZ: Maximum packet size<br />

The application must program this field with the maximum packet size for the current logical<br />

endpoint. This value is in bytes.<br />

Doc ID 13902 Rev 9 765/995

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