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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Debug support (DBG)<br />

RM0008<br />

Note:<br />

Important: Once Serial-Wire is selected using the dedicated ARM JTAG sequence, the<br />

boundary scan TAP is automatically disabled (JTMS forced high).<br />

Figure 322. JTAG TAP connections<br />

STM32F10xxx<br />

JNTRST<br />

JTMS<br />

SW-DP<br />

Selected<br />

TMS<br />

nTRST<br />

TMS<br />

nTRST<br />

JTDI<br />

TDI TDO TDI TDO<br />

JTDO<br />

Boundary scan<br />

TAP<br />

IR is 5-bit wide<br />

Cortex-M3 TAP<br />

IR is 4-bit wide<br />

ai14981<br />

29.6 ID codes <strong>and</strong> locking mechanism<br />

There are several ID codes inside the STM32F10xxx MCU. ST strongly recommends tools<br />

designers to lock their debuggers using the MCU DEVICE ID code located in the external<br />

PPB memory map at address 0xE0042000.<br />

29.6.1 MCU device ID code<br />

The STM32F10xxx MCU integrates an MCU ID code. This ID identifies the ST MCU partnumber<br />

<strong>and</strong> the die revision. It is part of the DBG_MCU component <strong>and</strong> is mapped on the<br />

external PPB bus (see Section 29.16 on page 971). This code is accessible using the JTAG<br />

debug port (4 to 5 pins) or the SW debug port (two pins) or by the user software. It is even<br />

accessible while the MCU is under system reset.<br />

958/995 Doc ID 13902 Rev 9

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