STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Debug support (DBG)
RM0008
29.6.2 Boundary scan TAP
JTAG ID code
The TAP of the STM32F10xxx BSC (boundary scan) integrates a JTAG ID code equal to:
●
●
●
●
29.6.3 Cortex-M3 TAP
In low-density devices:
– 0x06412041 = Revision A
In medium-density devices:
– 0x06410041 = Revision A
– 0x16410041 = Revision B and Revision Z
In high-density devices:
– 0x06414041 = Revision A
In connectivity line devices:
– 0x06418041 = Revision A and Revision Z
The TAP of the ARM Cortex-M3 integrates a JTAG ID code. This ID code is the ARM default
one and has not been modified. This code is only accessible by the JTAG Debug Port.
This code is 0x3BA00477 (corresponds to Cortex-M3 r1p1-01rel0, see Related documents
on page 1).
Only the DEV_ID(11:0) should be used for identification by the debugger/programmer tools.
29.6.4 Cortex-M3 JEDEC-106 ID code
The ARM Cortex-M3 integrates a JEDEC-106 ID code. It is located in the 4KB ROM table
mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF.
This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two
pins) or by the user software.
29.7 JTAG debug port
A standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five
data registers (for full details, refer to the Cortex-M3 r1p1 Technical Reference Manual
(TRM), for references, please see Related documents on page 1).
Table 200.
JTAG debug port data registers
IR(3:0) Data register Details
1111
1110
BYPASS
[1 bit]
IDCODE
[32 bits]
ID CODE
0x3BA00477 (ARM Cortex-M3 r1p1-01rel0 ID Code)
960/995 Doc ID 13902 Rev 9