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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Secure digital input/output interface (SDIO)<br />

Stream read (MultiMediaCard only)<br />

READ_DAT_UNTIL_STOP (CMD11) controls a stream-oriented data transfer.<br />

This comm<strong>and</strong> instructs the card to send its data, starting at a specified address, until the<br />

SDIO card host sends STOP_TRANSMISSION (CMD12). The stop comm<strong>and</strong> has an<br />

execution delay due to the serial comm<strong>and</strong> transmission <strong>and</strong> the data transfer stops after<br />

the end bit of the stop comm<strong>and</strong>. When the end of the memory range is reached while<br />

sending data <strong>and</strong> no stop comm<strong>and</strong> is sent by the SDIO card host, any subsequent data<br />

sent are considered undefined.<br />

The maximum clock frequency for a stream read operation is given by the following equation<br />

<strong>and</strong> uses fields of the card specific data register.<br />

Maximumspeed=<br />

MIN( TRANSPEED, -----------------------------------------------------------------------<br />

8 2readbllen –<br />

NSAC<br />

)<br />

TAAC R2WFACTOR<br />

● Maximumspeed = maximum read frequency<br />

● TRANSPEED = maximum data transfer rate<br />

● readbllen = maximum read data block length<br />

● writebllen = maximum write data block length<br />

● NSAC = data read access time 2 in CLK cycles<br />

● TAAC = data read access time 1<br />

● R2WFACTOR = write speed factor<br />

If the host attempts to use a higher frequency, the card is not able to sustain data transfer. If<br />

this happens, the card sets the UNDERRUN error bit in the status register, aborts the<br />

transmission <strong>and</strong> waits in the data state for a stop comm<strong>and</strong>.<br />

20.4.8 Erase: group erase <strong>and</strong> sector erase<br />

The erasable unit of the MultiMediaCard is the erase group. The erase group is measured in<br />

write blocks, which are the basic writable units of the card. The size of the erase group is a<br />

card-specific parameter <strong>and</strong> defined in the CSD.<br />

The host can erase a contiguous range of Erase Groups. Starting the erase process is a<br />

three-step sequence.<br />

First the host defines the start address of the range using the ERASE_GROUP_START<br />

(CMD35) comm<strong>and</strong>, next it defines the last address of the range using the<br />

ERASE_GROUP_END (CMD36) comm<strong>and</strong> <strong>and</strong>, finally, it starts the erase process by issuing<br />

the ERASE (CMD38) comm<strong>and</strong>. The address field in the erase comm<strong>and</strong>s is an Erase<br />

Group address in byte units. The card ignores all LSBs below the Erase Group size,<br />

effectively rounding the address down to the Erase Group boundary.<br />

If an erase comm<strong>and</strong> is received out of sequence, the card sets the ERASE_SEQ_ERROR<br />

bit in the status register <strong>and</strong> resets the whole sequence.<br />

If an out-of-sequence (neither of the erase comm<strong>and</strong>s, except SEND_STATUS) comm<strong>and</strong><br />

received, the card sets the ERASE_RESET status bit in the status register, resets the erase<br />

sequence <strong>and</strong> executes the last comm<strong>and</strong>.<br />

If the erase range includes write protected blocks, they are left intact <strong>and</strong> only nonprotected<br />

blocks are erased. The WP_ERASE_SKIP status bit in the status register is set.<br />

Doc ID 13902 Rev 9 475/995

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