STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Ethernet (ETH): media access control (MAC) with DMA controller
RM0008
Bit 9 RD: Retry disable
When this bit is set, the MAC attempts only 1 transmission. When a collision occurs on the
MII, the MAC ignores the current frame transmission and reports a Frame Abort with
excessive collision error in the transmit frame status.
When this bit is reset, the MAC attempts retries based on the settings of BL.
Note: This bit is applicable only in the Half-duplex mode.
Bit 8 Reserved
Bit 7 APCS: Automatic pad/CRC stripping
When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length’s
field value is less than or equal to 1 500 bytes. All received frames with length field greater
than or equal to 1 501 bytes are passed on to the application without stripping the Pad/FCS
field.
When this bit is reset, the MAC passes all incoming frames unmodified.
Bits 6:5 BL: Back-off limit
The Back-off limit determines the random integer number (r) of slot time delays (4 096 bit
times for 1000 Mbit/s and 512 bit times for 10/100 Mbit/s) the MAC waits before rescheduling a
transmission attempt during retries after a collision.
Note: This bit is applicable only to Half-duplex mode.
00: k = min (n, 10)
01: k = min (n, 8)
10: k = min (n, 4)
11: k = min (n, 1),
where n = retransmission attempt. The random integer r takes the value in the range 0 r < 2 k
Bit 4 DC: Deferral check
When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a
Frame Abort status, along with the excessive deferral error bit set in the transmit frame status
when the transmit state machine is deferred for more than 24 288 bit times in 10/100-Mbit/s
mode. Deferral begins when the transmitter is ready to transmit, but is prevented because of
an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter
defers for 10 000 bit times, then transmits, collides, backs off, and then has to defer again after
completion of back-off, the deferral timer resets to 0 and restarts.
When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS
signal goes inactive. This bit is applicable only in Half-duplex mode.
Bit 3 TE: Transmitter enable
When this bit is set, the transmit state machine of the MAC is enabled for transmission on the
MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of
the transmission of the current frame, and does not transmit any further frames.
Bit 2 RE: Receiver enable
When this bit is set, the receiver state machine of the MAC is enabled for receiving frames
from the MII. When this bit is reset, the MAC receive state machine is disabled after the
completion of the reception of the current frame, and will not receive any further frames from
the MII.
Bits 1:0 Reserved
908/995 Doc ID 13902 Rev 9