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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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Analog-to-digital converter (ADC)<br />

RM0008<br />

Figure 39.<br />

Alternate + Regular simultaneous<br />

1st trig<br />

ADC1 reg CH0 CH1 CH2<br />

CH0<br />

ADC1 inj<br />

CH2<br />

CH3<br />

CH3<br />

CH4<br />

ADC2 reg<br />

ADC2 inj<br />

CH3 CH5 CH6 CH6 CH7<br />

CH0<br />

CH7<br />

CH8<br />

synchro not lost<br />

2nd trig<br />

If a trigger occurs during an injected conversion that has interrupted a regular conversion, it<br />

will be ignored. Figure 40 shows the behavior in this case (2nd trig is ignored).<br />

Figure 40.<br />

Case of trigger occurring during injected conversion<br />

1st trig<br />

3rd trig<br />

ADC1 reg CH0 CH1 CH2<br />

ADC1 inj<br />

CH0<br />

CH2<br />

CH3<br />

CH3<br />

CH4<br />

CH0<br />

ADC2 reg<br />

ADC2 inj<br />

CH3 CH5 CH6 CH6 CH7<br />

CH0<br />

CH7<br />

CH8<br />

2nd trig<br />

4th trig<br />

11.9.9 Combined injected simultaneous + interleaved<br />

Note:<br />

It is possible to interrupt an interleaved conversion with an injected event. In this case the<br />

interleaved conversion is interrupted <strong>and</strong> the injected conversion starts, at the end of the<br />

injected sequence the interleaved conversion is resumed. Figure 41 shows the behavior<br />

using an example.<br />

When the ADC clock prescaler is set to 4, the interleaved mode does not recover with<br />

evenly spaced sampling periods: the sampling interval is 8 ADC clock periods followed by 6<br />

ADC clock periods, instead of 7 clock periods followed by 7 clock periods.<br />

Figure 41.<br />

ADC1<br />

ADC2<br />

Interleaved single channel with injected sequence CH11, CH12<br />

Sampling<br />

CH0 CH0 CH0<br />

Conversion<br />

CH0 CH0 CH0<br />

Trigger<br />

CH11<br />

CH12<br />

CH12<br />

CH11<br />

CH0<br />

CH0<br />

CH0<br />

CH0<br />

216/995 Doc ID 13902 Rev 9

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