STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

USB on-the-go full-speed (OTG_FS)
RM0008
Bits 1:0 FSLSPCS: FS/LS PHY clock select
When the core is in FS Host mode
01: PHY clock is running at 48 MHz
Others: Reserved
When the core is in LS Host mode
00: Reserved
01: PHY clock is running at 48 MHz.
10: PHY clock is running at 6 MHz. In USB 1.1 FS mode, use 6 MHz when the UTMIFS PHY
low power mode is selected and the PHY supplies a 6 MHz clock during LS mode. If you
select a 6 MHz clock during LS mode, you must do a soft reset.
11: Reserved
OTG_FS Host frame interval register (OTG_FS_HFIR)
Address offset: 0x404
Reset value: 0x0000 EA60
This register stores the frame interval information for the current speed to which the
OTG_FS controller has enumerated.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRIVL
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved
Bits 15:0 FRIVL: Frame interval
The value that the application programs to this field specifies the interval between two
consecutive SOFs (FS) or Keep-Alive tokens (LS). This field contains the number of PHY
clocks that constitute the required frame interval. The application can write a value to this
register only after the Port enable bit of the Host port control and status register (PENA bit in
OTG_FS_HPRT) has been set. If no value is programmed, the core calculates the value based
on the PHY clock specified in the FS/LS PHY Clock Select field of the Host configuration
register (FSLSPCS in OTG_FS_HCFG). Do not change the value of this field after the initial
configuration.
1 ms × (PHY clock frequency for FS/LS)
744/995 Doc ID 13902 Rev 9