STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Analog-to-digital converter (ADC)
Figure 34.
Regular simultaneous mode on 16 channels
Sampling
ADC1
ADC2
CH0 CH1 CH2 CH3
CH15 CH14 CH13 CH12
...
...
CH15
CH0
Conversion
Trigger
End of conversion on ADC1 and ADC2
11.9.3 Fast interleaved mode
This mode can be started only on a regular channel group (usually one channel). The
source of external trigger comes from the regular channel mux of ADC1. After an external
trigger occurs:
● ADC2 starts immediately and
● ADC1 starts after a delay of 7 ADC clock cycles.
If CONT bit is set on both ADC1 and ADC2 the selected regular channels of both ADCs are
continuously converted.
After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit
DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the
ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the
ADC1 converted data in the lower halfword.
Note:
The maximum sampling time allowed is